RT6219
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
capacitance can easily eliminate any excessive voltage
transients.
Four-Layer PCB
In any application with large quick transients, it should
calculate soar and sag to make sure that over-voltage
protection and under-voltage protection will not be triggered.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 6. Derating Curve of Maximum PowerDissipation
PD(MAX) = (TJ(MAX) − TA) / θJA
Layout Considerations
Layout is very important in high frequency switching
converter design. The PCB can radiate excessive noise
and contribute to converter instability with improper layout.
Certain points must be considered before starting a layout
using the RT6219.
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WDFN-10L 3x3 package, the thermal resistance, θJA, is
30.5°C/W on a standard JEDEC 51-7 four-layer thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by the following formula :
Make traces of the high current paths as short and wide
as possible.
Put the input capacitor as close as possible to the device
pins (VINand PGND).
The SW node encounters high frequency voltage swings
so it should be kept in a small area. Keep sensitive
components away from the SW node to prevent noise
coupling.
PD(MAX) = (125°C − 25°C) / (30.5°C/W) = 3.28W for
WDFN-10L 3x3 package
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance, θJA. The derating curve in Figure 6 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
The PGND pin should be connected to a strong ground
plane for heat sinking and noise protection.
Avoid using vias in the power path connections that have
switched currents (from CIN to PGND and CIN to VIN)
and the switching node (SW).
An example of PCB layout guide is shown in Figure 7
for reference.
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS6219-06 January 2018
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