RT6219
The next step is to select a proper capacitor for RMS
current rating. One good design uses more than one
capacitor with low Equivalent Series Resistance (ESR) in
parallel to form a capacitor bank. The input capacitance
value determines the input ripple voltage of the regulator.
The input voltage ripple can be approximately calculated
using the following equation :
slowly with respect to the IC's 500kHz switching frequency.
However, some modern digital loads can exhibit nearly
instantaneous load changes and the following section
shows how to calculate the worst-case voltage swings in
response to very fast load steps.
The amplitude of the ESR step up or down is a function of
the load step and the ESR of the output capacitor :
I
V
V
OUT
OUT
IN
V
(1
)
IN
VESR_STEP IOUT RESR
C
f
V
V
IN
IN SW
OUT
The amplitude of the capacitive sag is a function of the
load step, the output capacitor value, the inductor value,
the input-to-output voltage differential, and the maximum
duty cycle. The maximum duty cycle during a fast transient
is a function of the on-time and the minimum off-time since
the ACOTTM control scheme will ramp the current using
on-times spaced apart with minimum off-times, which is
as fast as allowed. Calculate the approximate on-time
(neglecting parasitics) and maximum duty cycle for a given
input and output voltage as :
The typical operating circuit is recommended to use two
10μF low ESR ceramic capacitors on the input.
Output Capacitor Selection
The RT6219 is optimized for ceramic output capacitors
and best performance will be obtained by using them. The
total output capacitance value is usually determined by
the desired output voltage ripple level and transient response
requirements for sag (undershoot on positive load steps)
and soar (overshoot on negative load steps).
VOUT
IN fSW
tON
tON
and DMAX
Output ripple at the switching frequency is caused by the
inductor current ripple and its effect on the output
capacitor's ESR and stored charge. These two ripple
components are called ESR ripple and capacitive ripple.
Since ceramic capacitors have extremely low ESR and
relatively little capacitance, both components are similar
in amplitude and both should be considered if ripple is
critical.
V
tON+ tOFF_MIN
The actual on-time will be slightly longer as the IC
compensates for voltage drops in the circuit, but we can
neglect both of these since the on-time increases
compensations for the voltage losses. Calculate the output
voltage sag as :
2
L(IOUT
)
VSAG
2COUT (VIN(MIN) DMAX VOUT
)
VRIPPLE VRIPPLE(ESR) VRIPPLE(C)
VRIPPLE(ESR) IL RESR
IL
The amplitude of the capacitive soar is a function of the
load step, the output capacitor value, the inductor value
VRIPPLE(C)
and the output voltage :
8COUT fSW
2
L(I
)
In addition to voltage ripple at the switching frequency,
the output capacitor and its ESR also affect the voltage
sag (undershoot) and soar (overshoot) when the load steps
up and down abruptly. The ACOT transient response is
very quick and output transients are usually small.
However, the combination of small ceramic output
capacitors (with little capacitance), low output voltages
(with little stored charge in the output capacitors), and
low duty cycle applications (which require high inductance
to get reasonable ripple currents with high input voltages)
increases the size of voltage variations in response to
very quick load changes. Typically, load changes occur
OUT
V
SOAR
2C
V
OUT
OUT
Most applications never experience instantaneous full load
steps and the RT6219's high switching frequency and fast
transient response can easily control voltage regulation
at all times. Therefore, sag and soar are seldom an issue
except in very low-voltage CPU core or DDR memory
supply applications, particularly for devices with high clock
frequencies and quick changes into and out of sleep
modes. In such applications, simply increasing the amount
of ceramic output capacitor (sag and soar are directly
proportional to capacitance) or adding extra bulk
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14
DS6219-06 January 2018
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
