RT6218A/B
V
= V
V
RIPPLE(C)
V
OUT
RIPPLE
RIPPLE(ESR)
V
= I R
RIPPLE(ESR)
L
ESR
I
L
V
=
R1
C
RIPPLE(C)
FF
8C
f
OUT SW
FB
RT6218A/B
For the Typical Operating Circuit for 1.2V output and an
inductor ripple of 0.6A, with 2 x 22F output capacitance
each with about 5m ESR including PCB trace
resistance, the output voltage ripple components are :
R2
GND
Figure 1. CFF Capacitor Setting
Enable Operation (EN)
V
= 0.6A5m = 3mV
RIPPLE(ESR)
0.6A
844μF650kHz
V
=
= 2.62mV
RIPPLE(C)
For automatic start-up the EN pin can be connected to
VIN, through a 100k resistor. Its large hysteresis
band makes EN useful for simple delay and timing
circuits. EN can be externally pulled to VIN by adding a
resistor-capacitor delay (REN and CEN in Figure 2).
Calculate the delay time using EN's internal threshold
where switching operation begins.
V
= 3mV + 2.62mV = 5.62mV
RIPPLE
Feed-Forward Capacitor (CFF)
The RT6218A/B is optimized for ceramic output
capacitors and for low duty-cycle applications. This
optimization makes circuit stability easy to achieve with
reasonable output capacitors, but it also narrows the
optimization of transient responses of the converter.
For high output voltage (that is, high duty-cycle)
applications, the FB voltage is highly attenuated from
the output, the circuit's response becomes
under-damped and transient response is slowed. A
small feedforward capacitor (CFF) can be introduced
into the feedback network to speed up the transient
response of high output voltage circuits. The
feedforward capacitor is added across the upper FB
divider resistor (as seen in Figure 1) to speed up the
transient response without affecting the steady-state
stability of the circuit.
An external MOSFET can be added to implement
digital control of EN when no system voltage above 2V
is available (Figure 3). In this case, a 100k pull-up
resistor, REN, is connected between VIN and the EN
pin. MOSFET Q1 will be under logic control to pull
down the EN pin. To prevent enabling circuit when VIN
is smaller than the VOUT target value or some other
desired voltage level, a resistive voltage divider can be
placed between the input voltage and ground and
connected to EN to create an additional input under
voltage lockout threshold (Figure 4).
EN
R
EN
V
EN
RT6218A/B
IN
To optimize transient response, a CFF value is chosen
so that the gain and phase boost of the feedback
network increases the bandwidth of the converter,
while still maintaining an acceptable phase margin.
Generally, larger CFF values provide higher bandwidth,
but may result in an unacceptable phase margin or
instability. Suitable feedforward capacitor values can
be chosen from the table of Suggested Component
Values.
C
EN
GND
Figure 2. External Timing Control
R
EN
100k
V
EN
RT6218A/B
GND
IN
Q1
Enable
Figure 3. Digital Enable Control Circuit
Copyright © 2018 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
14
DS6218A/B-01 October 2018
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
