RT6203E
Ceramic capacitors are ideal for switching regulator
applications due to its small, robust and very low ESR.
However, care must be taken when these capacitors are
used at the input. A ceramic input capacitor combined
with trace or cable inductance forms a high quality (under
damped) tank circuit. If the RT6203E circuit is plugged
into a live supply, the input voltage can ring to twice its
nominal value, possibly exceeding the device's rating. This
situation is easily avoided by placing the low ESR ceramic
input capacitor in parallel with a bulk capacitor with higher
ESR to damp the voltage ringing.
If ceramic capacitors are used as the output capacitors,
both the components need to be considered due to the
extremely low ESR and relatively small capacitance.
Output Transient Undershoot and Overshoot
In addition to voltage ripple at the switching frequency,
the output capacitor and its ESR also affect the voltage
sag (undershoot) and soar (overshoot) when the load steps
up and down abruptly. TheACOTTM transient response is
very quick and output transients are usually small. The
following section shows how to calculate the worst-case
voltage swings in response to very fast load steps.
The input capacitor should be placed as close as possible
to the VIN pins, with a low inductance connection to the
GND of the IC. In addition to a larger bulk capacitor, a
small ceramic capacitors of 0.1μF should be placed close
to the VINandGNDpin. This capacitor should be 0402 or
0603 in size.
The output voltage transient undershoot and overshoot each
have two components : the voltage steps caused by the
output capacitor's ESR, and the voltage sag and soar due
to the finite output capacitance and the inductor current
slew rate. Use the following formulas to check if the ESR
is low enough (typically not a problem with ceramic
capacitors) and the output capacitance is large enough to
prevent excessive sag and soar on very fast load step
edges, with the chosen inductor value.
Output Capacitor Selection
The RT6203E are optimized for ceramic output capacitors
and best performance will be obtained using them. The
total output capacitance value is usually determined by
the desired output voltage ripple level and transient response
requirements for sag (undershoot on load apply) and soar
(overshoot on load release).
The amplitude of the ESR step up or down is a function of
the load step and the ESR of the output capacitor :
VESR _STEP = ΔIOUT x RESR
The amplitude of the capacitive sag is a function of the
load step, the output capacitor value, the inductor value,
the input-to-output voltage differential, and the maximum
duty cycle. The maximum duty cycle during a fast transient
is a function of the on-time and the minimum off-time since
the ACOTTM control scheme will ramp the current using
on-times spaced apart with minimum off-times, which is
as fast as allowed. Calculate the approximate on-time
(neglecting parasites) and maximum duty cycle for a given
input and output voltage as :
Output Ripple
The output voltage ripple at the switching frequency is a
function of the inductor current ripple going through the
output capacitor's impedance. To derive the output voltage
ripple, the output capacitor with capacitance, COUT, and
its equivalent series resistance, RESR, must be taken into
consideration. The output peak-to-peak ripple voltage
VRIPPLE, caused by the inductor current ripple ΔIL, is
characterized by two components, which are ESR ripple
VRIPPLE(ESR) and capacitive ripple VRIPPLE(C), can be
expressed as below :
VOUT
IN fSW
tON
tON
=
and DMAX =
V
tON tOFF_MIN
The actual on-time will be slightly longer as the IC
compensates for voltage drops in the circuit, but we can
neglect both of these since the on-time increase
compensates for the voltage losses. Calculate the output
VRIPPLE = VRIPPLE(ESR) VRIPPLE(C)
VRIPPLE(ESR) = IL RESR
IL
VRIPPLE(C)
=
8COUT fSW
voltage sag as :
2
L(I
)
OUT
V
SAG
=
2C
V
D
V
MAX OUT
OUT
IN(MIN)
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is a registered trademark of Richtek Technology Corporation.
DS6203E-00 January 2019
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