RT5771A
Thermal Shutdown (OTP)
conductivity four-layer test board. The maximum power
dissipation at TA = 25°C can be calculated as below :
The device implements an internal thermal shutdown
function when the junction temperature exceeds 150°C.
The thermal shutdown forces the device to stop switching
when the junction temperature exceeds the thermal
shutdown threshold. Once the die temperature decreases
below the hysteresis of 20°C, the device reinstates the
power up sequence.
PD(MAX) = (125°C − 25°C) / (70°C/W) = 1.429W for a
WDFN-10L 3x3 package.
The maximum power dissipation depends on the operating
ambient temperature for the fixed TJ(MAX) and the thermal
resistance, θJA. The derating curves in Figure 2 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Thermal Considerations
The junction temperature should never exceed the
absolute maximum junction temperature TJ(MAX), listed
under Absolute Maximum Ratings, to avoid permanent
damage to the device. The maximum allowable power
dissipation depends on the thermal resistance of the IC
package, the PCB layout, the rate of surrounding airflow,
and the difference between the junction and ambient
temperatures. The maximum power dissipation can be
calculated using the following formula :
Layout Considerations
Layout is very important in high frequency switching
converter design. The PCB can radiate excessive noise
and contribute to converter instability with improper layout.
Certain points must be considered before starting a layout
using the RT5771A.
Make the traces of the main current paths as short and
wide as possible.
Put the input capacitor as close as possible to the device
PD(MAX) = (TJ(MAX) − TA) / θJA
pins (VIN andGND).
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction-to-ambient
thermal resistance.
SW node encounters high frequency voltage swings so
it should be kept in a small area. Keep sensitive
components away from the SW node to prevent stray
capacitive noise pick-up.
For continuous operation, the maximum operating junction
temperature indicated under Recommended Operating
Conditions is 125°C. The junction-to-ambient thermal
resistance, θJA, is highly package dependent. For a
WDFN-10L 3x3 package, the thermal resistance, θJA, is
70°C/W on a standard JEDEC 51-7 high effective-thermal-
Ensure all feedback network connections are short and
direct. Place the feedback network as close to the chip
as possible.
TheGNDpin and Exposed Pad should be connected to
a strong ground plane for heat sinking and noise
protection.
1.5
1.4
Four-Layer PCB
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
An example of PCB layout guide is shown in Figure 3
for reference.
SW should be connected to
inductor by wide and short trace.
Keep sensitive components away
from this trace.
The voltage divider must
be connected as close to
the device as possible.
R1
V
OUT
R2
R
EN
1
2
3
4
5
10
9
EN
PGOOD
NC
SW
FB
VCC
VIN
GND
GND
C
V
IN
IN2
R
PGOOD
L
8
C
IN1
7
V
OUT
11
6
SW
C
OUT
GND
0
25
50
75
100
125
Input capacitor must be placed
as close to the IC as possible.
The output capacitor must
be placed near the IC.
Ambient Temperature (°C)
Figure 2.Derating Curve of Maximum PowerDissipation
Figure 3. PCB Layout Guide
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
12
DS5771A-02 June 2019
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
