RT5771A
Input Capacitor Selection
For a given output voltage sag specification, the ESR value
can be determined.
High quality ceramic input decoupling capacitor, such as
X5R or X7R, with values greater than 10μF are
recommended for the input capacitor. The X5R and X7R
ceramic capacitors are usually selected for power regulator
capacitors because the dielectric material has less
capacitance variation and more temperature stability.
Another parameter that has influence on the output voltage
sag is the equivalent series inductance (ESL). The rapid
change in load current results in di/dt during transient.
Therefore, the ESL contributes to part of the voltage sag.
Using a capacitor with low ESL can obtain better transient
performance. Generally, using several capacitors
connected in parallel can have better transient performance
than using a single capacitor for the same total ESR.
Voltage rating and current rating are the key parameters
when selecting an input capacitor. Generally, selecting an
input capacitor with voltage rating 1.5 times greater than
the maximum input voltage is a conservatively safe design.
Unlike the electrolytic capacitor, the ceramic capacitor has
relatively low ESR and can reduce the voltage deviation
during load transient. However, the ceramic capacitor can
only provide low capacitance value. Therefore, use a mixed
combination of electrolytic capacitor and ceramic capacitor
to obtain better transient performance.
The input capacitor is used to supply the input RMS
current, which can be approximately calculated using the
following equation :
V
V
V
OUT
V
IN
OUT
I
= I
1
IN_RMS
LOAD
IN
Power Good Output (PGOOD)
The next step is selecting a proper capacitor for RMS
current rating. One good design is using more than one
capacitor with low equivalent series resistance (ESR) in
parallel to form a capacitor bank.
PGOODis an open-drain type output and requires a pull-
up resistor. PGOOD is actively held low in soft-start,
standby, and shutdown. It is released when the output
voltage rises above 90% of nominal regulation point. The
PGOOD signal goes low if the output is turned off or is
10% below its nominal regulation point.
The input capacitance value determines the input ripple
voltage of the regulator. The input voltage ripple can be
approximately calculated using the following equation :
Under-Voltage Protection (UVP)
IOUT(MAX) 0.25
V
=
IN
The output voltage can be continuously monitored for under
voltage. When under-voltage protection is enabled, both
UGATE and LGATE gate drivers will be forced low if the
output is less than 33% of its set voltage threshold. The
UVP will be ignored for at least 3ms (typ.) after start up or
a rising edge on the ENthreshold. Toggle ENthreshold or
cycle VIN to reset the UVP fault latch and restart the
controller.
CIN fSW
Output Capacitor Selection
The output capacitor and the inductor form a low pass
filter in the buck topology. In steady state condition, the
ripple current flowing into/out of the capacitor results in
ripple voltage. The output voltage ripple (VP-P) can be
calculated by the following equation :
1
Over-Current Protection (OCP)
VP_P = LIRILOAD(MAX) ESR +
8COUT fSW
The RT5771A provides over-current protection by detecting
high-side MOSFET peak inductor current. If the sensed
peak inductor current is over the current limit threshold,
the OCP will be triggered. When OCP is tripped, the
RT5771A will keep the over current threshold level until
the over current condition is removed.
When load transient occurs, the output capacitor supplies
the load current before the controller can respond.
Therefore, the ESR will dominate the output voltage sag
during load transient. The output voltage undershoot (VSAG
)
can be calculated by the following equation :
VSAG = ILOAD ESR
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS5771A-02 June 2019
www.richtek.com
11
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