RT5509
Parameter
Clock Data Fall Time
Clock Data Rise Time
Spike Suppression Time
Symbol
t
F
t
R
t
SP
(Note 5)
0.7x
DVDD
--
10
10
10
10
--
--
--
--
--
--
--
--
--
0.3x
DVDD
--
--
--
--
8
V
V
ns
ns
ns
ns
ns
Test Conditions
Min
20
20
--
Typ
--
--
--
Max
300
300
50
Unit
ns
ns
ns
I
2
S Interface Electrical Characteristics
High-Level Input Voltage
Low-Level Input Voltage
Setup Time, LRCK to SCLK
Rising Edge
V
IH
V
IL
t
su1
Hold Time, LRCK from SCLK
t
h1
Rising Edge
Setup Time, SDIN to SCLK
Rising Edge
Hold Time, SDIN from SCLK
Rising Edge
Rise/Fall Time for
SCLK/LRCLK
t
su2
t
h2
t
r
Note 1.
Continuously stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Note 2.
JA
is measured under natural convection (still air) at T
A
= 25C with the component mounted on a high
effective-thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard.
Note 3.
Devices are ESD sensitive. Handling precaution recommended.
Note 4.
The device is not guaranteed to function outside its operating conditions.
Note 5.
Guaranteed by design.
Note 6.
The switching terminal should be used within AC peak limits. Overshoot and undershoot must be less than 100ns.
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation
DS5509-01
September
2017
www.richtek.com
7
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
