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RT5509 参数 Datasheet PDF下载

RT5509图片预览
型号: RT5509
PDF下载: 下载PDF文件 查看货源
内容描述: [暂无描述]
分类和应用:
文件页数/大小: 58 页 / 3081 K
品牌: RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
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RT5509
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
DAC to Stereo Speaker Amplifier
Signal to Noise Ratio
SNR
PVDD = 9.5V, THD+N < 1%, Gain =
12dB, A-Weighting
Gain = 0dB, A-Weighting
Noise level
Vn
Gain = 12dB, A-Weighting
Gain = 18dB, A-Weighting
1kHz, PVDD = 3.6V, 8 load + 22H,
THD + N = 1%
1kHz, PVDD = 9.5V, 8 load + 22H,
THD + N = 1%
1kHz, Po = 350mW, 8 load + 22H
217Hz ripple = 200mVpp
I
Q_VBAT
Normal operation, DSP, speaker
protection bypassed
Normal operation, DSP, speaker
protection bypassed
Normal operation, DSP, speaker
protection activated
P
O
= 2.5W, including DC to DC
converter, 100Hz audio signal
(Note 5)
0.7 x
DVDD
--
--
I
PULLUP
= 3mA
--
--
1.3
0.6
0.6
0.6
225
0
100
1.3
0.6
--
--
2
--
--
--
--
--
--
--
--
--
--
--
--
0.3 x
DVDD
--
0.4
400
--
--
--
--
--
900
--
--
--
V
92
15
35
55
0.6
4.2
90
85
1
6
12
70
100
20
40
60
0.65
4.3
75
75
3
12
18
76
108
25
45
65
0.7
W
4.4
50
65
5
18
mA
24
80
%
dB
dB
mA
V
dB
Maximum Output Power
Po
THD+N
PSRR
Quiescent Current (VBAT)
Quiescent Current (DVDD)
I
Q_DVDD
Output Power Efficiency
η
I
2
C Interface Electrical Characteristics
V
IH
SDA, SCL Input Threshold
V
IL
Pull-Down Current
Digital Output Low (SDA)
Clock Operating Frequency
I
FO2
V
OL
f
SCL
A
V
kHz
s
s
s
s
ns
ns
ns
s
s
Bus Free Time Between Stop
t
BUF
and Start Condition
Hold Time After (Repeated)
Start Condition
Repeated Start Condition
Setup Time
Stop Condition Time
Data Hold Time
Input Data Hold Time
Data Setup Time
Clock Low Period
Clock High Period
t
HD,STA
t
SU,STA
t
SU,STD
t
HD,DAT
(OUT)
t
HD,DAT
(IN)
t
SU,DAT
t
LOW
t
HIGH
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation
www.richtek.com
6
DS5509-01
September
2017