RT5112A
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Thermal Considerations
Four-Layer PCB
The junction temperature should never exceed the
absolute maximum junction temperature TJ(MAX), listed
under Absolute Maximum Ratings, to avoid permanent
damage to the device. The maximum allowable power
dissipation depends on the thermal resistance of the IC
package, the PCB layout, the rate of surrounding airflow,
and the difference between the junction and ambient
temperatures. The maximum power dissipation can be
calculated using the following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
0
25
50
75
100
125
Ambient Temperature (°C)
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction-to-ambient
thermal resistance.
Figure 10. Derating Curve of Maximum PowerDissipation
Layout Considerations
For continuous operation, the maximum operating junction
temperature indicated under Recommended Operating
Conditions is 125°C. The junction-to-ambient thermal
resistance, θJA, is highly package dependent. For a WL-
CSP-25B 2.2x2.3 (BSC) package, the thermal resistance,
θJA, is 31.5°C/W on a standard JEDEC 51-7 high effective-
thermal-conductivity four-layer test board. The maximum
power dissipation at TA = 25°C can be calculated as below
:
The PCB layout is an important step to maintain the high
performance of the RT5112A. Both the high current and
the fast switching nodes demand full attention to the PCB
layout to keep the robustness of the RT5112A through
the PCB layout. Improper layout might lead to the
symptoms of poor line or load regulation, ground and output
voltage shifts, stability issues, unsatisfying EMI behavior
or worsened efficiency. For the best performance of the
RT5112A, the following PCB layout guidelines must be
strictly followed.
PD(MAX) = (125°C − 25°C) / (32.7°C/W) = 3.05W for a WL-
CSP-25B 2.2x2.3 (BSC) package.
The trace from switching node to inductor should be as
short as possible to minimized the switching loop for
better EMI.
The maximum power dissipation depends on the operating
ambient temperature for the fixed TJ(MAX) and the thermal
resistance, θJA. The derating curves in Figure 10 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Place the input and output capacitors close to the input
and output pins respectively for good filtering.
Keep the main power traces as wide and short as
possible.
Connect the AGND, DGND, GNDB1 and GNDB2 to a
strong ground plane for maximum thermal dissipation
and noise protection.
Directly connect the Buck output capacitors to the
feedback network to avoid bouncing caused by parasitic
resistance and inductance from the PCB trace.
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60
DS5112A-02 August 2019
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
