RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
7:6 Reserved
00
RW Reserved
Interrupt reflash pulse width timing.
00 : disable (default)
RW 01 : 2s
INT_DEG[
5:4
00
1:0]
10 : 4s
11 : 8s
Indicate PMU's State
0000 : IDLE (default)
0x42
INT_SET
0001 : ONSEQ (slot1 to slot7 + 4ms, when 4ms
clock end will tigger ONSEQ_END)
0010 : ONSEQ_END
SEQ_STA
3:0
0000
R
T[2:0]
0011 : ENSEQ
0100 : OFFSEQ
0101 : OFFSEQ_END (slot7 to slot1, when slot1
sequence end will tigger OFFSEQ_END)
1111 : Else
Addr
RegName
Bit
BitName
Default Type
Description
BST latch off (BSTEN)
0 : Release (default)
1 : Latch off
BST latch off (HWEN)
0 : Release (default)
1 : Latch off
BCK1 latch off
0 : Release (default)
1 : Latch off
BCK2 latch off
0 : Release (default)
1 : Latch off
PMU_
STAT
0x43 PMU_STAT 7:0
00000000
R
LDO1 latch off
0 : Release (default)
1 : Latch off
LDO2 latch off
0 : Release (default)
1 : Latch off
LDO3 latch off
0 : Release (default)
1 : Latch off
LDO4 latch off
0 : Release (default)
1 : Latch off
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS5112A-02 August 2019
www.richtek.com
59
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
