RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
Set slot period :
00 : 2.73ms
01 : 1.365ms
10 : 0.682ms (default)
11 : 0.341ms
(slot period is the base unit of each SLOT, for
example SLOT2 = 2*slot period; SLOT3 = 3*slot
period)
Set soft-start time slew rate (Buck_SR) :
00 : 1mV/s
RW 01 : 2mV/s
SEQ_SPE
ED[1:0]
7:6
10
10 : 4mV/s (default)
11 : 7mV/s
(Buck's VOUT min. step = 12.5mV, f = 2.5MHz)
(Once slot period is chose, corresponding soft start
time slew rate is determined.)
Note : Buck soft-start time (Buck_tss)
00 : 1ms/V x Vout
0x09 SEQ_PROG
01 : 0.5ms/V x Vout
10 : 0.25ms/V x Vout (default)
11 : 0.143ms/V x Vout
2 bits to control LDOs and Buck's ON/OFF
00 : Power-Down, relative regulators (CHx_DELAY
≠ 3’b000) disable by power off sequence, others
turn off by each EN bit
SEQ_
CTRL[1:0]
01 : Power-UP,relative regulators (CHx_DELAY ≠
3’b000) enable by power on sequence, others turn
on by each EN bit
5:4
10
RW
10 : All regulators's ON/OFF depend on each EN
bit. (default)
11 : All regulators turn off directly.
3:0 Reserved
0000
RW Reserved
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS5112A-02 August 2019
www.richtek.com
41
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
