RT5112A
Application Information
When the RT5112A recovers from OTP, it can re-start in
three configurations with register 0x0A[4:3] bits.
The RT5112A is a smart power-management integrated
circuit (PMIC), which includes two Buck converters and
four LDOs.
0x0A[4:3] = 00, the RT5112A is manual re-start with
default register values.
System Under-Voltage Protection and Over-Voltage
Protection
0x0A[4:3] = 01, the RT5112A is auto recovery with last
register values before OTP.
The device does not operate with VSYS voltages below the
Under-Voltage Lock Out (UVLO) level. There is a typical
100mV hysteresis implemented to avoid unstable on/ off
behavior. The RT5112A is initialized in its default state
after VSYS voltage recovers from UVLO. When VSYS voltage
reaches the Over Voltage Protection level, the RT5112A
will disable Buck converter immediately to protect next
stage circuit input. The VSYS UV and OV status bits and
interrupt bits will be set, and INTRB pin will be pulled low
with corresponding to protection detected.
0x0A[4:3] = 10, the RT5112A is latched off. Re-set VIN
or HWEN to re-start the RT5112A with default register
values.
Enable and Disable Control
The HWEN pin controls the RT5112A start up without
enabling channels. If HWEN pin is at low state, the
RT5112Ais in power down mode and I2C will returnNACK
to any request. Only when HWEN pin is at high state, all
channels are controllable via I2C with corresponding
ENABLE command. There is a built-in resistor on HWEN
pin to keep at low state if the pin is left unconnected.
Thermal Protection
The RT5112Afeatures over-temperature warning (OTW)
and over-temperature protection (OTP). The OTW status
bit and interrupt bit are set and INTRB pin will be pulled
low when the junction temperature is higher than typical
125°C. If the junction temperature further exceeds typical
160°C, OTP will be triggered to shut down the device.
The below tables provide channels state with combinations
of different ENABLE pins and register EN bits.
Sequence Control Setting
The RT5112A sequence on/off control setting can be
programmed via I2C with dedicated registers as below.
Table 1. Buck and LDOs Control
EN bits SEQ_CTRL bits Dependent
HWEN pin
Low
SEQ bits
000
On / Off
Off
0
1
0
1
0
1
0
1
No
No
Low
000
Off
Low
000
No
Off
Low
000
No
Off
High
High
High
High
000
No
Off
000
No
On
000
Yes
CTRL
On
000
On / Off
Note : CTRL indicates several operating conditions as below.
(1) SEQ_CTRL[1:0] = 00, set SEQ bits
regardless EN bit.
000 and EN bit = 1, channel is turned off after 7 sequence slot count
(2) SEQ_CTRL[1:0] = 01, set SEQ bits000 and EN bit = 1, channel is turned on depends on EN bit.
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is a registered trademark of Richtek Technology Corporation.
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22
DS5112A-02 August 2019
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
