欢迎访问ic37.com |
会员登录 免费注册
发布采购

RT5090E 参数 Datasheet PDF下载

RT5090E图片预览
型号: RT5090E
PDF下载: 下载PDF文件 查看货源
内容描述: [暂无描述]
分类和应用:
文件页数/大小: 41 页 / 534 K
品牌: RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
 浏览型号RT5090E的Datasheet PDF文件第1页浏览型号RT5090E的Datasheet PDF文件第2页浏览型号RT5090E的Datasheet PDF文件第4页浏览型号RT5090E的Datasheet PDF文件第5页浏览型号RT5090E的Datasheet PDF文件第6页浏览型号RT5090E的Datasheet PDF文件第7页浏览型号RT5090E的Datasheet PDF文件第8页浏览型号RT5090E的Datasheet PDF文件第9页  
RT5090E
Pin No.
Pin Name
Pin Function
BUCK1 enable and current limit setting (CS) input. Connect a resistor to
GND to set the threshold for BUCK1 synchronous R
DS(ON)
sense. The GND
to PHASE1 current limit threshold is 1/12th the voltage seen at CS over a
0.515V to 3V range. Leave CS floating or drive it above 4.5V to shutdown
BUCK1.
Voltage detection for depop function. Connect to Input Power or Standby
Power Ratio Voltage.
Device Power Supply. Internal LDO Supply from VIN1 or External Power
Supply. With 4.7F MLCC to AGND, as close as possible to VCC pin.
Analog ground.
Connect to capacitor. Hold up capacitors to keep enough energy to supply
control logic when remove input power for depop function.
Enable control. The power on of rails when this pin be pulled high, vice
versa.
The rails alive or turn-off in sleep mode (DC OFF) can by register 0x08
setting.
Reset signal for SOC.
Clock input for the I
2
C interface.
Data line for the I
2
C interface.
Power input for LDO. Input Capacitors as close as possible to VIN_LDO pin.
Power ground. Connect to GND.
31
ENTRIP
32
33
34
35
VDET
VCC
AGND
VCAP
36
EN_CTRL
37
38
39
40
SOC_REST
SCL
SDA
VIN_LDO
41 (Exposed Pad) PGND
Copyright
©
2018 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS5090E-00 August 2018
www.richtek.com
3