RT5035A/B
Place a ceramic capacitor for noise filtering from
RTCPWR to RTCGND with short connections.
Place the C32K (logic output signal) output so that
the return ground current runs back to RTCGND. Do
not route the trace close to the oscillator input.
The ground surrounded C32K pin and
keep away from noisy devices.
LX should be connected to Inductor by wide and short
trace, keep sensitive compontents away from this trace.
VOUT_CH3
GND
BAT
VOUT_CH1
GND
GND
Backup
Battery
COUT1
COUT1
RRTCPWR
CVDDM
CRTCPWR
CIN3
CXIN CXOUT
CIN1
Y1
COUT3
L3
L1
40 39 38 37 36 35 34 33 32 31
LX1
/RESET
FB7
1
2
30 LX3
CIN8
REXT
VOUT_CH1
CIN5
29 PVDD8
28 VOUT8
D6
D5
D4
D3
COUT8
VOUT_CH8
3
COUT6
CIN6/7
4
27 VOUT5/FB5
26 PVDD5
25 LX5
VOUT6
GND
D2
D1
BAT PVDD6
5
BAT
COUT7
L7
GND
LX7
LX4
6
VOUT_CH5
L5
D7
L4
COUT5
BAT
7
24 PVDD2
23 LX2A
22 EN
VOUT_CH4
Input/Output
CIN2
COUT4
capacitors must be
placed as close as
possible to the
8
BAT PVDD4/10
CIN4
L10
LX10
9
VOUT_CH10
L2
Input/Output pins.
COUT10
10
21 LX2B
VNEG
CVNEG
11 12 13 14 15 16 17 18 19 20
CCP
CSWO
COUT2
COUT2
GND
GND
SWO
VOUT_CH2
Connect the
Exposed Pad to
a ground plane.
Figure 2. PCB Layout Guide
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is a registered trademark of Richtek Technology Corporation.
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40
DS5035A/B-03 February 2020
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
