RT5035A/B
Thermal Considerations
Layout Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature.
The maximum power dissipation can be calculated by
the following formula :
The PCB layout is an important step to maintain the
high performance of the RT5035A/B. Both the high
current and the fast switching nodes demand full
attention to the PCB layout to save the robustness of
the RT5035A/B through the PCB layout. Improper
layout might show the symptoms of poor line or load
regulation, ground and output voltage shifts, stability
issues, unsatisfying EMI behavior or worsened
efficiency. For the best performance of the RT5035A/B,
the following PCB layout guidelines must be strictly
followed.
PD(MAX) = (TJ(MAX) TA) / JA
where TJ(MAX) is the maximum junction temperature,
TA is the ambient temperature, and JA is the junction to
ambient thermal resistance.
Place the input and output capacitors as close as
possible to the input and output pins respectively for
good filtering.
For recommended operating condition specifications,
the maximum junction temperature is 125C. The
junction to ambient thermal resistance, JA, is layout
dependent. For WQFN-40L 5x5 package, the thermal
resistance, JA, is 27.5C/W on a standard JEDEC
51-7 four-layer thermal test board. The maximum
power dissipation at TA = 25C can be calculated by
the following formula :
Keep the main power traces as wide and short as
possible.
The switching node area connected to LX and
inductor should be minimized for lower EMI.
Place the feedback components as close as possible
to the FB pin and keep these components away from
the noisy devices.
PD(MAX) = (125C 25C) / (27.5C/W) = 3.63W for
WQFN-40L 5x5 package
The maximum power dissipation depends on the
operating ambient temperature for fixed TJ(MAX) and
thermal resistance, JA. The derating curve in Figure 1
allows the designer to see the effect of rising ambient
temperature on the maximum power dissipation.
Connect the GND and Exposed Pad to a strong
ground plane for maximum thermal dissipation and
noise protection.
Directly connect the output capacitors to the
feedback network of each channel to avoid bouncing
caused by parasitic resistance and inductance from
the PCB trace.
4.0
Four-Layer PCB
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
For the 32-kHz oscillator to the best performance,
observe the following guidelines :
Place the crystal and its components close to the
oscillator side and the oscillator pins.
Ensure that the ground plane under the oscillator and
its components are of good quality.
Avoid placing a separate ground under the oscillator
and connecting it to the general ground through a
single point.
0
25
50
75
100
125
Ambient Temperature (°C)
Avoid long connections to the crystal and to the load
capacitor that create a large loop on the PCB.
Figure 1. Derating Curve of Maximum Power
Dissipation
Use a short connection between the two crystal load
capacitors and route the common connection to the
oscillator ground reference.
Copyright © 2020 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS5035A/B-03 February 2020
www.richtek.com
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