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RT5035A 参数 Datasheet PDF下载

RT5035A图片预览
型号: RT5035A
PDF下载: 下载PDF文件 查看货源
内容描述: [暂无描述]
分类和应用:
文件页数/大小: 44 页 / 2881 K
品牌: RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
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RT5035A/B  
RTC time read/write method :  
When reading RTC time via I2C interface, suggest read 6 bytes (address A11 to A16) together and finish reading  
within 0.5 second to avoid the second carry issue. A16.RTCT_SEC[0] can be used for checking whether second is  
carried during reading time. When writing RTC time via I2C interface, suggest to write 6 bytes (address A11 to A16)  
together. A11 is first and then A12, A13, A14, A15, A16. Suggest finishing writing within 0.5 second to avoid second  
carry issue during writing.  
Output Voltage Ramp Rate  
For instance, CH3 VCORE output voltage ramp up rate = 1.5 x 0.8V / 4ms = 0.3V/ms. The ramp up/down rate is kept  
the same for enabling soft-start or dynamic output voltage adjustment.  
Each channel has different ramp rate as listed below.  
1.3V  
Ramp rate =  
1.5 x 0.8V/4ms  
1.1V  
Ramp rate = 1.5 x  
0.8V/4ms  
0V  
0.7ms  
3.7ms  
Note :  
About Dynamic Voltage Scaling, CH1, CH3, CH4, CH8, CH10 output voltage can be changed without inrush and  
Vout ramping control when they have been turned on (said, dynamically change Vout). CH2, CH5, CH6 are not.  
Synchronization and Spread Spectrum  
If SYNC remains logic high or low, the spread spectrum clock will act the main clock for PWM. And, spread spectrum  
function can be turned off by register A15.SS.  
If the toggling clock of SYNC is detected, the PLL clock will act the main clock for PWM and the clock of PLL will  
track its frequency. And the division ratio is decided by A15.SYN_DIV.  
Furthermore, according to the logic high and low level threshold voltage, both 1.8V and 3V logic are compatible. If it  
isn't used, the SYNC pin must be connected to GND.  
VDDM  
SYNC  
ASIC  
CLK  
Spread Spectrum  
Clock Generator  
Detection  
0
1
Clock for PWM  
synchronization  
A15.SS  
The output interface  
of ASIC : Push-Pull  
is preferred.  
DIV  
A15.SYN_DIV  
PLL  
If the clock of SYNC is 12MHz, VDDM is not recommended as pull-up power voltage. Other power domains can be  
used if they fit the logic high and logic low threshold voltage.  
Copyright © 2020 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
DS5035A/B-03 February 2020  
www.richtek.com  
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