RF2495
Pin
1
Function Description
Interface Schematic
Supply voltage for the LNA, bias circuits, and control logic. External RF
VCC1
bypassing is required. The trace length between the pin and the bypass
capacitors should be minimized. The ground side of the bypass capaci-
tors should connect immediately to ground plane.
RF Input pin. This pin is internally matched for optimum noise figure
from a 50Ω source. This pin is internally DC-biased and, if connected
to a device with DC present, should be blocked with a capacitor suit-
able for the frequency of operation.
VBIAS
2
LNA_IN
LNA IN
GND1
Ground connection. For best performance, keep traces physically short
and connect immediately to ground plane.
3
4
5
GND2
GND1
ATTN
Ground connection for the LNA circuits. For best performance, keep
traces physically short and connect immediately to ground plane.
See pin 2.
Attenuation pin. A logic high reduces LNA gain by 15dB.
VCC
ATTN
GND2
LNA Output pin. This pin requires a connection to V through an
inductor.
6
7
LNA OUT
SOURCE
CC
LNA OUT
Connection to source of MOSFET transistor used as mixer. Drain and
source are symmetric.
DRAIN
GATE
SOURCE
Connection to drain of MOSFET transistor used as mixer.
See pin 7.
See pin 7.
8
9
DRAIN
GATE
Connection to gate of MOSFET transistor used as mixer. Internally
DC-biased. Use DC-blocking capacitor.
Power control. A logic “low” turns the part off. A logic “high” (>1.6V)
turns the part on.
10
PD
VCC
PD
GND2
This diode structure is used to provide electrostatic discharge protec-
tion to 3kV using the Human body model. The following pins are pro-
tected: 1, 3, 5, 9, 10.
ESD
VCC
Rev A4 030220
8-283
RFMD [ RF MICRO DEVICES ]
