RF2053
Programming Registers
Register Map Diagram
Data
Reg.
R/W
Add
Name
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
PLL1x0
15
14
13 12 11 10
TVCO
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00
01
02
03
04
05
08
LD_EN LD_LEV
MIX1_IDD
TKV1
PDP LF_ACT
CPL
Res
Res
CT_POL Res EXT_VCO FULLD CP_LO_I
MIX1_VB MIX2_IDD
TKV2
MIX2_VB
KV_RNG NBR_CT_AVG NBR_KV_AVG
FLL_FACT CT_CPOLREFSTBY
CLK_DIV_BYPASS
LO1_I
XO_CT
XO_I2 XO_I1 XO_CR_S
TCT
T_PH_ALGN
Res
LO2_I
SU_WAIT
P1_VCOSEL P1_CT_E P1_KV_E P1_LO-
Res
P1_CP_DEF
N
N
DIV
PLL1x1
PLL1x2
PLL1x3
PLL1x4
PLL1x5
PLL2x0
R/W
R/W
R/W
R/W
R/W
R/W
09
0A
0B
0C
0D
10
P1_NUM_MSB
P1_NUM_LSB
P1_N
P1_CT_DEF
Res
Res
Res
P1_CT_GAIN
Res
P1_VCOI
P1_KV_GAIN
P1_CT_V
P2_CP_DEF
P1_DN
P1_N_PHS_ADJ
P2_KV__E
P2_VCOSEL P2_CT_E
P2_LO-
DIV
Res
N
N
PLL2x1
PLL2x2
PLL2x3
PLL2x4
PLL2x5
GPO
R/W
R/W
R/W
R/W
R/W
R/W
11
12
13
14
15
18
P2_NUM_MSB
P2_NUM_LSB
P2_N
P2_CT_DEF
Res
Res
Res
P2_VCOI
P2_DN
P2_CT_GAIN
Res
P2_KV_GAIN
P2_CT_V
P2_N_PHS_ADJ
Res
P1_G- Res P1_ P1_
Res
P2_G-
PO1
Res
P2_G- P2_
Res
PO1
GPO GPO
PO3 GPO
4
3
4
CHIPREV
RB1
R
R
R
R
R
19
1C
1D
1E
1F
PARTNO
REVNO
LOCK
TEN
CT_CAL
V0_CAL
RSM_STATE
TMUX
CP_CAL
Res
RB2
V1_CAL
Res
DACTEST
RB3
TEST
CPU CPD FNZ LDO TSEL Res
Res
_BY
P
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DS140110
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