RF2053
Start-up
When starting up and following device reset then REFSTBY=0, REFSTBY should be asserted high approximately 500ecs.
before ENBL is taken high. This is to allow the XO to settle and will depend on XO characteristics. After taking ENBL high there
is typically 20usecs for the PLL state machine and charge pump to initialize, the VCO warm-up state, before PLL locking starts.
The time spent in the VCO warm-up state is set by CFG1:TVCO, which should be set to 00111 when using a 26MHz clock. Fol-
lowing the warm-up period there will be the additional time taken for the PLL to settle to the required frequency. All of these
timings will be dependent upon application specific factors such as loop filter bandwidth, reference clock frequency, and XO
characteristics. The fastest turn-on and lock time will be obtained by leaving REFSTBY asserted high, disabling all calibration
routines (always the case for the RF2053), minimizing the VCO warm-up time, and setting the PLL loop bandwidth as wide as
possible.
The device can be reset into its initial state (default settings) at any time by performing a hard reset. This is achieved by setting
the RESETB pin low for at least 100ns.
Setting Up Device Operation
The device offers a number of operating modes which need to be set up in the device before it will work as intended. This is
achieved as follows.
Set-up device
operation
1
To set up RF2053 operation w ith an external VCO it is
necessary to set the EXT_VCO bit in CFG 1 register high
and to alw ays select VCO3 to route the VCO input
through to the synthesizer. The LF_ACT bit in CFG 1
Program
EXT_VCO=1
P2_VCOSEL=10
LF_ACT=0
register should be set to
norm ally used in the loop filter.
0 as an external op-am p is
W hen setting up the device it is necessary to decide if
an active or passive loop filter w ill be used in the
phase locked loop. Set the phase detector polarity bit
in CFG 1 since the active filter inverts the loop filter
voltage. Norm ally active loop filter w ith an external op-
Active loop
filter?
N o
PDP set to 0
am p is used w ith the RF2053, so set PD P
default setting.
= 1, the
D efault
The m ixer linearity setting is then selected. The default
value is w ith being the low est setting and the
highest. The M IX2_ID D bits are located in the CFG 2
register.
M ixer
linearity
Program
M IX2_IDD
4
1
5
Internal
capacitors
used to set
Xtal load
The internal crystal loading capacitors are also
program m ed to present the correct load to the crystal.
The capacitance internal to the chip can be varied
from 8-16pF in 0.25pF steps (default=10pF). The
reference divider m ust also be set to determ ine the
phase detector frequency (default=1). These bits are
located in the CFG 4 register.
Program XO_CT,
XO_CR_S and
CLK_D IV
Set-up com plete
2
Three registers need to be written, taking 3.9us at the maximum clock speed.
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