Preliminary
SC3042B
•
•
•
•
•
Quartz SAW Frequency Stability
Fundamental Fixed Frequency
Very Low Jitter and Power Consumption
Rugged, Miniature, Surface-Mount Case
Low-Voltage Power Supply (3.3 VDC)
This digital clock is designed for use in high-speed communications timing systems. Fundamental-mode
oscillation is made possible by surface-acoustic-wave (SAW) technology. The design results in low jitter,
compact size, and low power consumption. Differential outputs provide a sine wave that is capable of driving
50
Ω
loads.
624.0 MHz
Differential
Sine-Wave
Clock
Absolute Maximum Ratings
Rating
Power Supply Voltage (V
CC
at Terminal 1)
Input Voltage (ENABLE at Terminal 8)
Case Temperature (Powered or Storage)
Value
0 to +4.0
0 to +4.0
-40 to +85
Units
VDC
VDC
°C
SMC-8 Case
Electrical Characteristics
Characteristic
Output Frequency
Q and Q Output
Absolute Frequency
Tolerance from 624.0 MHz
Voltage into 50Ω (VSWR
≤
1.2)
Operating Load VSWR
Symmetry
Harmonic Spurious
Nonharmonic Spurious
Q and Q Period Jitter
Output (Disabled)
No Noise on V
CC
200 mV
P-P
from 1 MHz to �½ f
O
on
Amplitude into 50
Ω
V
IH
V
IL
I
IH
I
IL
t
PD
V
CC
I
CC
T
A
1, 3
1, 3
+3.13
0
+3.30
20
RFM SC3042B 624.00 MHz YYWW
3, 9
Sym
f
O
Δf
O
V
O
Notes
1, 2
1, 3
3, 4, 5
3, 4, 6
3, 4, 6, 7
3, 4, 7, 8
3, 9
3
Minimum
623.875
0.60
49
Typical
Maximum
624.125
±200
1.1
2:1
51
-30
-60
Units
MHz
ppm
V
P-P
%
dBc
dBc
ps
P-P
ps
P-P
mV
P-P
KΩ
V
V
mA
mA
ms
VDC
mA
°C
15
30
35
75
Output DC Resistance (between Q & Q)
ENABLE (Terminal 14)
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Propagation Delay
DC Power Supply
Operating Voltage
Operating Current
Operating Ambient Temperature
Lid Symbolization (YY = Year, WW = Week)
50
V
CC
-0.1
0.0
3
V
CC
V
CC
+0.1
0.20
5
-1
1
+3.47
40
+70
CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.
NOTES:
1.
2.
3.
4.
5.
Unless otherwise noted, all specifications include any combination of load
VSWR, VCC, and TA. In addition, Q and Q are terminated into 50
Ω
loads
to ground. (See: Typical Test Circuit.)
One or more of the following United States patents apply: 4,616,197;
4,670,681; 4,760,352.
The design, manufacturing process, and specifications of this device are
subject to change without notice.
Only under the nominal conditions of 50
Ω
load impedance with VSWR
≤
1.2 and nominal power supply voltage.
Symmetry is defined as the pulse width (in percent of total period)
measured at the 50% points of Q or Q. (See: Timing Definitions.)
6.
Jitter and other spurious outputs induced by externally generated electrical
noise on V
CC
or mechanical vibration are not included. Dedicated external
voltage regulation and careful PCB layout are recommended for optimum
performance.
Applies to period jitter of Q and Q. Measurements are made with the
Tektronix CSA803 signal analyzer with at least 1000 samples.
Period jitter measured with a 200 mV
P-P
sine wave swept from 1 MHz to
one-half of f
O
at the V
CC
power supply terminal.
The outputs are enabled when Terminal 8 is at logic HIGH. Propagation
delay is defined as the time from the 50% point on the rising edge of
ENABLE to the 90% point on the rising edge of the output amplitude or as
the fall time from the 50% point to the 10% point. (SEE: Timing
Definitions.)
7.
8.
9.
www.RFM.com
E-mail: info@rfm.com
©2008 by RF Monolithics, Inc.
Page 1 of 2
SC3042B - 3/27/08
RFM [ RF MONOLITHICS, INC ]
