• Clk_Idle_End - indicates the time from the beginning of the frame till the end of the idle period. This time
is given in multiples of PCM clock periods. The delta between Clk_Idle_Start and Clk_Idle_End is the
clock idle period, e.g., for PCM clock rate = 1 MHz, frame sync period = 10 kHz, Clk_Idle_Start = 60,
Clk_Idle_End = 90. Between each two-frame sync there are 70 clock cycles (instead of 100). The clock
idle period starts 60 clock cycles after the beginning of the frame and lasts 90-60=30 clock cycles. This
means that the idle period ends 100-90=10 clock cycles before the end of the frame. The data transmis-
sion must end prior to the beginning of the idle period.
Audio Encoding
The DR-WLS1273L-102 CODEC interface can use one of four audio coding patterns:
• A-Law (8-bit)
• m-Law (8-bit)
• Linear (8 or 16-bit)
• Transparent
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Page 8 of 31
DR-WLS1273L-102 Data Sheet - 12/13/12
RFM [ RF MONOLITHICS, INC ]
