•
Baseband Processor
– IEEE Std 802.11n single-stream data rates (MCS0-7) and SGI support
•
2.4/5.8 GHz Radio
– Digital Radio Processor (DRP) implementation
– Integrated LNA
– Supports IEEE Std 802.11a/b/g and 802.11n
DR-WLS1273L-102 Bluetooth Features
• V4.0 + EDR, Power Class 1.5 + BLE
• Bluetooth Qualified Design Listing: B017988
• BT Enhanced Data Rates - 2 and 3 Mbps
• Enhanced UART host interface
• Very low power consumption
•
On-chip Embedded radio
– Integrated 2.4 GHz RF transceiver
– All digital PLL transmitter with digitally controlled oscillator
– Near-zero IF architecture
– On-chip TX/RX switch
– Support for Class-1.5 applications
•
Embedded ARM microprocessor system
– High rate four wire UART HCI (H4) and three wire UART HCI (H5)
– Automatic clock-detection mechanism
• Flexible PCM interface - full flexibility for data order, sampling and positioning
• Temperature detection and compensation mechanism ensures minimal variation in the RF performance
over the entire operating temperature range
• Low-power scan achieves paging and inquiry scans at 1/3 normal power
• Digital Radio Processor (DRP) single-ended 50 ohm I/O for easy RF interfacing
• Patch trap mechanism and reserved RAM enables easy bug fixes
• Advance Audio Interfaces and capabilities
– A2DP support
– A2DP internal loopback
– Wide-band speech support
– On board SBC encoder/decoder - offloads host for A2DP and wide-band speech processing
– Full support for Bluetooth low energy (BLE) standard. BLE can operate in parallel with standard
Bluetooth function.
WLAN Functional Blocks
The DR-WLS1273L-102 WLAN architecture includes a digital radio processor and a point-to-multipoint
baseband core function. The architecture is based on a single-processor ARM core. The device includes
on-chip peripherals to enable easy communication between a host system and the WLAN core function.
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© 2012 by RF Monolithics, Inc.
Technical support +1.972.448.3700
E-mail:
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DR-WLS1273L-102 Data Sheet - 12/13/12