R5F2L387BNFP 参数 Datasheet PDF下载

Under development

Preliminary specification

Specifications in this manual are tentative and subject to change.

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,

R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

5. Resets

5.5

Watchdog Timer Reset

When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its pins,

CPU, and SFRs when the watchdog timer underflows. Then the program beginning with the address indicated by

the reset vector is executed. The low-speed on-chip oscillator clock with no division is automatically selected as the

CPU clock after reset.

Refer to

for the status of the SFRs after watchdog timer reset.

The internal RAM is not reset. When the watchdog timer underflows, the contents of internal RAM are undefined.

The underflow period and refresh acknowledge period for the watchdog timer can be set by bits WDTUFS0 and

WDTUFS1 and bits WDTRCS0 and WDTRCS1 in the OFS2 register, respectively.

Refer to

for details of the watchdog timer.

5.6

Software Reset

When the PM03 bit in the PM0 register is set to 1 (MCU reset), the MCU resets its pins, CPU, and SFRs. The

program beginning with the address indicated by the reset vector is executed. The low-speed on-chip oscillator

clock with no division is automatically selected for the CPU clock after reset.

Refer to

for the status of the SFRs after software reset.

The internal RAM is not reset.

REJ09B0441-0010 Rev.0.10

Page 58 of 809

Jul 30, 2008