Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
5. Resets
5.4
Voltage Monitor 0 Reset
A reset is applied using the on-chip voltage detection 0 circuit. The voltage detection 0 circuit monitors the input
voltage to the VCC pin. The voltage to monitor is Vdet0. The Vdet0 voltage detection level can be changed by the
settings of bits VDSEL0 and VDSEL1 in the OFS register.
When the input voltage to the VCC pin reaches the Vdet0 level or below, the pins, CPU, and SFRs are reset.
When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock
starts counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held high
and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock with no
division is automatically selected as the CPU clock after a reset.
The LVDAS bit in the OFS register can be used to select whether voltage monitor 0 reset is enabled or disabled
after a reset. The setting of the LVDAS bit is enabled at all resets.
To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to
0, bits VW0C0 and VW0C6 bits in the VW0C register to 1 individually, and the VCA25 bit in the VCA2 register to
1.
Bits VDSEL0 to VDSEL1 and LVDAS cannot be changed by a program. To set these bits, write values to b4 to b6
of address 0FFFFh using a flash programmer.
Refer to
for details of the OFS register.
Refer to
for the status of the SFRs after voltage monitor 0 reset.
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet0 level or below while
writing to the internal RAM is in progress, the contents of internal RAM are undefined.
Refer to
for details of voltage monitor 0 reset.
VCC
4.7 kΩ
(reference)
RESET
tw(Vdet0)
VCC
V
det0
Vccmin
V
por1
Sampling time
(1, 2)
Internal reset signal
(low valid)
1
f
OCO-S
×
32
Notes:
1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation
voltage range (1.8 V or above) during the sampling time.
2. The sampling clock can be selected. Refer to
6. Voltage Detection Circuit
for details.
3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit.
Refer to
6. Voltage Detection Circuit
for details.
4. Refer to
36. Electrical Characteristics.
5. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in
the OFS register to 0, bits VW0C0 and VW0C6 in the VW0C register to 1 individually, and
the VCA25 bit in the VCA2 register to 1.
Figure 5.7
Example of Voltage Monitor 0 Reset Circuit and Operation
Jul 30, 2008
REJ09B0441-0010 Rev.0.10
Page 57 of 809
RENESAS [ RENESAS TECHNOLOGY CORP ]
