Preliminary document
Specifications in this document are tentative and subject to change.
Under development
R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group
1. Overview
1.3
Block Diagram
Figure 1.5 shows a Block Diagram.
8
8
5
1
8
6
8
Port P0
Port P1
I/O ports
Peripheral functions
Port P2
Port P3
Port P4
Port 6
System clock
generation circuit
A/D converter
(10 bits × 12 channels)
Timers
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
Timer RA (8 bits)
Timer RB (8 bits)
Timer RC (16 bits)
Timer RD
UART or
clock synchronous serial I/O
(8 bits × 2 channels)
(16 bits × 2)
Timer RE (8 bits)
CAN module (3)
(1 channel)
SSU
(8 bits × 1 channel)
LIN module
(1 channel)
DTC
Watchdog timer
(14 bits)
Memory
R8C CPU core
ROM (1)
R0H
R1H
R0L
R1L
SB
USP
ISP
INTB
PC
FLG
R2
R3
RAM (2)
A0
A1
FB
Multiplier
Notes:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
3. Only in the R8C/34W Group and R8C/34X Group.
Figure 1.5
Block Diagram
REJ03B0312-0010 Rev.0.10
Apr 09, 2010
Page 14 of 67
RENESAS [ RENESAS TECHNOLOGY CORP ]
