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R5F21134DFP 参数 Datasheet PDF下载

R5F21134DFP图片预览
型号: R5F21134DFP
PDF下载: 下载PDF文件 查看货源
内容描述: 16位单片机M16C族/ R8C / Tiny系列 [16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY/R8C/Tiny SERIES]
分类和应用: 微控制器和处理器外围集成电路计算机时钟
文件页数/大小: 224 页 / 2076 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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R8C/13 Group  
12.3 Timer (Timer Z)  
Timer Y, Z mode register  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
TYZMR  
Address  
008016  
After reset  
00  
2
1
1
1
Bit symbol  
TYMOD0  
Function  
RW  
RW  
Bit name  
Timer Y-related bit  
R1EDG  
RW  
RW  
TYWC  
TYS  
RW  
RW  
b5 b4  
Timer Z operation  
mode bit  
1 1 : Programmable wait one-shot generation  
mode  
TZMOD0  
TZMOD1  
RW  
RW  
RW  
Timer Z write  
control bit  
Must set to "1" in programmable wait one-shot  
generation mode  
TZWC  
TZS  
Timer Z count  
start flag  
0 : Stops counting  
1 : Starts counting  
NOTES:  
1. When the TZS bit is set to "0" (stop counting), the timer reloads the content of the reload register before it stops.  
Read out the count value before you stop the timer.  
Timer Y, Z waveform output control register  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
PUM  
Address  
008416  
After reset  
0016  
0
0
0 0  
Bit symbol  
Bit name  
Reserved bit  
RW  
RW  
Function  
Must set to 0”  
(b3-b0)  
TYOPL  
Timer Y-related bit  
RW  
RW  
0 : Outputs "H" level one-shot pulse.  
Outputs "L" when the timer is stopped.  
1 : Outputs "L" level one-shot pulse  
Outputs "H" when the timer is stopped.  
Timer Z output level  
latch  
TZOPL  
INT0 pin one-shot trigger  
control bit(2)  
0 : INT0 pin one-shot trigger disabled  
1 : INT0 pin one-shot trigger enabled(2)  
INOSTG  
INOSEG  
RW  
RW  
INT0 pin one-shot trigger  
polarity select bit(1)  
0 : Edge trigger at falling edge  
1 : Edge trigger at rising edge  
NOTES:  
1. The INOSEG bit is valid only when the INT0PL bit in the INTEN register is set to "0" (one-edge).  
2. The INOSGT bit must be set to 1after the INT0EN bit the INOSEG register and the INOSEG bit in the PUM register are set.  
When setting the INOSTG bit to "1" (INT0 pin one-shot trigger enabled), the INT0F0 and INT0F1 bits in the INT0F register  
must be set.  
The INOSTG bit must be set to 0(INT0 pin one-shot trigger disabled) after the TZS bit in the TYZMR register is set to 0”  
(count stop).  
Figure 12.26 TYZMR Register and PUM Register in Programmable Wait One-shot Generation Mode  
Rev.1.20 Jan 27, 2006 page 99 of 205  
REJ09B0111-0120  
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