R1LP0408C-I Series
Low V
CC
Data Retention Characteristics
(Ta =
−40
to +85°C)
Parameter
V
CC
for data retention
Data
retention
current
−5SI
to +85°C
to +70°C
to +40°C
to +25°C
−7LI
to +85°C
to +70°C
to +40°C
to +25°C
Chip deselect to data retention time
Operation recovery time
Symbol Min Typ
V
DR
I
CCDR
I
CCDR
I
CCDR
I
CCDR
I
CCDR
I
CCDR
I
CCDR
I
CCDR
t
CDR
t
R
0
4
Max Unit Test conditions*
10
8
V
µA
µA
µA
µA
µA
µA
µA
µA
ns
ns
3
2
CS#
≥
V
CC
−
0.2 V, Vin
≥
0 V
V
CC
= 3.0 V, Vin
≥
0 V
CS#
≥
V
CC
−
0.2 V
1.0*
2
3
0.8*
1
3
20
16
1.0*
2
10
0.8*
1
10
See retention waveform
t
RC
*
Notes: 1. Typical values are at V
CC
= 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
2. Typical values are at V
CC
= 3.0 V, Ta = +40°C and specified loading, and not guaranteed.
3. CS# controls address buffer, WE# buffer, OE# buffer, and Din buffer. In data retention mode,
Vin levels (address, WE#, OE#, I/O) can be in the high impedance state.
4. t
RC
= read cycle time.
Low V
CC
Data Retention Timing Waveform
(CS# Controlled)
t
CDR
V
CC
4.5 V
Data retention mode
t
R
2.2 V
V
DR
CS#
0V
CS#
≥
V
CC
– 0.2 V
Rev.2.00, May.26.2004, page 12 of 12
RENESAS [ RENESAS TECHNOLOGY CORP ]
