M66310P/FP
Switching Characteristics
(V
CC
=
5V)
Limits
Item
Maximum clock frequency
Low-level to high-level and
high-level to low-level
output propagation time
(CK
S
-SQ
P
)
High-level to low-level
output propagation time (R-
SQ
P
)
High-level to low-level
output propagation time (R-
Q
A
to Q
P
)
Low-level to high-level and
high-level to low-level
output propagation time
(CK
L
−Q
A
to Q
P
)
Output enable time to low-
level and high-level
(OE−Q
A
to Q
P
)
Input Capacitance
Output Capacitance
Power dissipation
(Note 1)
Capacitance
Note:
Symbol
f
max
t
PLH
t
PHL
Min
5
—
—
Ta
=
25°C
Typ
—
—
—
Max
—
100
100
Ta
= −40
to
+85°C
Min
Max
4
—
—
—
130
130
Unit
MHz
ns
ns
Conditions
C
L
=
50 pF
R
L
=
1 kΩ
(Note 2)
t
PHL
—
—
100
—
130
ns
t
PHZ
—
—
150
—
200
ns
t
PZH
t
PHZ
—
—
—
—
100
150
—
—
130
200
ns
ns
t
PZH
t
PHZ
C
I
C
O
C
PO
—
—
—
—
—
—
—
—
—
11
100
150
10
15
—
—
—
—
—
—
130
200
10
15
—
ns
ns
pF
pF
pF
OE
=
V
CC
1. C
PD
is the internal capacitance of the IC calculated from operation supply current under no-load conditions.
(per latch)
The power dissipated during operation under no–load conditions is calculated using the following formula:
2
P
D
=
C
PD
•
V
CC
•
f
I
+
I
CC
•
V
CC
Timing Requirements
(V
CC
=
5 V)
Limits
Item
CK
S
, CK
L
,
R
pulse width
A setup time with respect to
CK
S
CK
S
setup time with respect
to CK
L
A hold time with respect to
CK
S
R,
recovery time with
respect to CK
S
, CK
L
Symbol
t
w
t
su
t
su
t
h
t
rec
Min
100
100
100
10
50
Ta
=
25°C
Typ
—
Max
—
Ta
= −40
to
+85°C
Min
Max
130
130
130
15
70
—
Unit
ns
ns
ns
ns
ns
Conditions
(Note 2)
REJ03F0176-0201 Rev.2.01 Mar 31, 2008
Page 6 of 9
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