M66310P/FP
Logic Diagram
Parallel data outputs
Q
A
1
Q
B
2
Q
C
24
Q
D
23
Q
E
22
Q
F
21
Q
G
20
Q
H
19
Q
I
18
Q
J
17
Q
K
16
Q
L
15
Q
M
14
Q
N
13
Q
O
11
Q
P
12
Serial data
output
SQ
P
V
CC
10
3
0
CK
D R
0
CK
D R
0
CK
D R
0
CK
D R
0
CK
D R
0
CK
D R
0
CK
D R
0
CK
D R
0
CK
D R
0
CK
D R
0
CK
D R
0
CK
D R
0
CK
D R
0
CK
D R
0
CK
D R
0
CK
D R
1
CK
D R
1
CK
D R
1
CK
D R
1
CK
D R
1
CK
D R
1
CK
D R
1
CK
D R
1
CK
D R
1
CK
D R
1
CK
D R
1
CK
D R
1
CK
D R
1
CK
D R
1
CK
D R
1
CK
D R
1
CK
D R
5
4
8
7
6
9
A
OE
Enable Serial
input data
input
V
CC
Parallel
data output
V
CC
Serial data
output
CK
S
CK
L
GND
R
Shift Direct Latch
clock reset clock
input input input
Output format
Pin Arrangement
M66310P/FP
Parallel data
outputs
Q
A
←
1
Q
B
←
2
V
CC
3
Q
A
Q
B
Q
C
Q
D
Q
E
24
→
Q
C
23
→
Q
D
22
→
Q
E
21
→
Q
F
20
→
Q
G
19
→
Q
H
18
→
Q
I
17
→
Q
J
16
→
Q
K
15
→
Q
L
14
→
Q
M
13
→
Q
N
Serial data input
Enable input
A
→
4
OE
→
5
A
OE
CK
L
R
CK
S
Q
F
Q
G
Q
H
Q
I
Q
J
Q
K
Latch clock input CK
L
→
6
Direct reset input
R
→
7
Parallel data
outputs
Shift clock input CK
S
→
8
GND
9
Serial data output SQ
P
←
10
Parallel data
outputs
Q
O
←
11
Q
P
←
12
SQ
P
Q
O
Q
P
Q
L
Q
M
Q
N
(Top view)
Outline: PRDP0024AA-A (24P4D)
(24P2N-B)
REJ03F0176-0201 Rev.2.01 Mar 31, 2008
Page 2 of 9
RENESAS [ RENESAS TECHNOLOGY CORP ]
