MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(2-1) Interrupt Enable Register 0 (Address : 10h)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BEMPE
VBSE RSME SOFE DVSE CTRE
INTNE INTRE URST SADR SCFG SUSP WDST RDST CMPL SERR
Reset
Bit
Bit
15
14
Name
Function
W/R
W/R
W/R
Name
VBSE
H/W S/W USB
Vbus interrupt
enable
0 : Disable
1 : Enable
0
0
0
0
-
-
Resume interrupt 0 : Disable
RSME
SOFE
DVSE
CTRE
enable
1 : Enable
SOF interrupt
enable
0 : Disable
1 : Enable
13
12
11
W/R
W/R
W/R
0
0
0
0
0
0
-
-
-
Device state
0 : Disable
1 : Enable
interrupt enable
Control transfer
interrupt enable
0 : Disable
1 : Enable
Endpoint5-0 buffer
empty/size error
interrupt enable
0 : Disable
1 : Enable
10
9
BEMPE
INTNE
W/R
W/R
0
0
0
0
-
-
Endpoint5-0 buffer
not ready
0 : Disable
1 : Enable
interrupt enable
Endpoint5-0 buffer
ready
0 : Disable
1 : Enable
8
7
INTRE
URST
W/R
W/R
0
0
0
0
-
-
interrupt enable
USB reset detect If this bit is "1", then the DVST flag is set when detected USB reset.
Set Address
6
5
4
SADR
SCFG
SUSP
If this bit is "1", then the DVST flag is set after executed SetAddress.
execute
W/R
W/R
W/R
0
0
0
0
0
0
-
-
-
Set Configration
If this bit is "1", then the DVST flag is set after executed SetConfigration.
execute
Suspend
If this bit is "1", then the DVST flag is set when detected suspend.
detect
Control write
If this bit is "1", then the CTRT flag is set when shifted to status stage
3
WDST
transfer status
in control write transfer.
stage
W/R
0
0
-
Control read
If this bit is "1", then the CTRT flag is set when shifted to status stage
2
1
0
RDST
CMPL
SERR
transfer status
in control read transfer.
stage
W/R
W/R
W/R
0
0
0
0
0
0
-
-
-
Control transfer
complete
If this bit is "1", then the CTRT flag is set when control transfer
completed (when the status stage completed normally).
Control transfer
sequence error
If this bit is "1" then the CTRT flag is set when error
occurred in the sequence of control transfer.
13
RENESAS [ RENESAS TECHNOLOGY CORP ]
