MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
(2) Interrupts
There are eight f actors of interrupt to CPU.
When interrupt occurred, the f actor can be known to
ref er to "Interrupt Status Register 0" and "Interrupt
Status Register 1".
These interrupts can be set of its enable/disable
independently to set "Interrupt Enable Register 0"
and "Interrupt Enable Register 1".
If disable is set, interrupt is not occurred but interrupt
status f lag is set.
Each f actor of interrupt is shown in the table below,
and also describes below the interrupt conditions and
how to deal with the interrupt.
Resume detect interrupt (RESM)
If dev ice state is in suspended state and resume interrupt
enable f lag is set, interrupt occurs when USB bus state
is changed ("J" to "K" or "SE0").
This interrupt can be occurred ev en if the internal
clock(sck) is halted. To clear the status f lag, set the
internal clock(sck) in operation and then write "0". If the
internal clock(sck) is halted, status f lag can not be
cleared.
SOF detect interrupt (SOFR)
Interrupt occurs when detect SOF.
Vbus (connect/shut down) interrupt (VBUS)
Interrupt occurs when Vbus input state is changed
(both "L" to "H" and "H" to "L").
To know Vbus input state, conf irm the Vbus bit of
interrupt status register 0. Conf irmation of Vbus bit
must be done af ter enabled internal clock operation.
This interrupt can be occurred ev en if the internal
clock(sck) is halted. To clear the status f lag, enables
the internal clock(sck) in operation and then write "0".
If the internal clock(sck) is halted, status f lag can not
be cleared.
This interrupt is usef ul to detect connect/shut-down of
USB f or prepareration/close of USB transf ers.
Device state transition interrupt (DVST)
M66290A manages the dev ice state by H/W.
It manages Powered, Def ault, Address, Conf igured, and
Suspended state. Dev ice state can be known to ref er to
"Interrupt Status Register 0".
As to dev ice state shif t, see the item of "Dev ice state
shif t" in "(3) Control transf er/emulation" in the latter part.
Dev ice state transition interrupt occurs when dev ice state
shif ted. The number of f actors is f our, that is, USB bus
reset detect, suspend detect, execution of "Set Address",
and execution of "Set Conf iguration".
USB reset is detected when SE0 state ov er 2.5us is
continued on D+, D- terminal.
Suspend is detected when idle state ov er 3ms is
continued on D+, D- terminal.
Summary of interrupts
Status bit
VBUS
RESM
SOFR
DVST
CTRT
Name
Vbus interrupt
(connec/shut-down detect)
Resume detect interrupt
SOF detect interrupt
dev ice state transition
interrupt
Control transf er
stage transition interrupt
Endpoint buf f er
empty /size-ov er interrupt
Endpoint buf f er not ready
interrupt
Endpoint buf f er ready
interrupt
Abstract of interrupt f actor
Change of the Vbus input
(both "L" to "H" and "H" to "L")
Resume signal receiv ed in suspended
Receiv ed SOF
Shif t of dev ice state
Stage shif t of control transf er
In each endpoint, when data transmit of all buf f er
is ended and buf f er is empty , or in OUT transf er,
receiv ed packet which exceeds max packet size.
When buf f er is in not ready state (SIE cannot read
and write) to IN/OUT token of each endpoint.
When buf f er of each endpoint became ready
(read enable/write enable)
DVSQ[2:0]
CTSQ[2:0]
Relational status bit
Vbus
BEMP
EPB_EMP_OVR[5:0]
INTN
INTR
EPB_NRDY [5:0]
EPB_RDY [5:0]
10
RENESAS [ RENESAS TECHNOLOGY CORP ]
