M66282FP
Variable Length Delay Bit
1 Line (8192 Bits) Delay
Input data can be written at the rising edge of WCK after write cycle and output data is read at the rising edge of RCK
before read cycle to easily make 1 line delay.
8192 cycle 8193 cycle 8194 cycle
(0')
(1')
(2')
0 cycle
1 cycle
2 cycle
8190 cycle 8191 cycle
WCK
RCK
t
RESS
t
RESH
WRESB
RRESB
t
DS
t
DH
t
DS
t
DH
Dn
(0)
(1)
(2)
(8189)
(8190)
(8191)
(0')
(1')
(2')
(3')
8192 cycle
t
AC
t
OH
Qn
(0)
(1)
(2)
(3)
WEB, REB = "L"
n-bit Delay Bit
(Reset at cycles according to the delay length)
n
−
2 cycle n
−
1 cycle
n cycle
(0')
n + 1 cycle
n + 2 cycle n + 3 cycle
(1')
(2')
(3')
0 cycle
1 cycle
2 cycle
WCK
RCK
t
RESS
t
RESH
t
RESS
t
RESH
WRESB
RRESB
t
DS
t
DH
t
DS
t
DH
Dn
(0)
(1)
(2)
(n
−
3)
(n
−
2)
(n
−
1)
(0')
(1')
(2')
(3')
m cycle
t
AC
t
OH
Qn
(0)
(1)
(2)
(3)
WEB, REB = "L"
REJ03F0255-0200 Rev.2.00 Sep 14, 2007
Page 9 of 13
RENESAS [ RENESAS TECHNOLOGY CORP ]
