M66282FP
n-bit Delay 2
(Slides input timings of WRESB and RRESB at cycles according to the delay length)
0 cycle
1 cycle
2 cycle
n
−
2 cycle n
−
1 cycle
n cycle
n
+
1 cycle n
+
2 cycle n
+
3 cycle
WCK
RCK
t
RESS
t
RESH
WRESB
t
RESS
t
RESH
RRESB
t
DS
t
DH
t
DS
t
DH
Dn
(0)
(1)
(2)
(n
−
2)
(n
−
1)
(n)
(n +1)
(n +2)
(n +3)
m cycle
t
AC
t
OH
Qn
(0)
(1)
(2)
(3)
WEB, REB = "L"
m
≥
3
n-bit Delay 3
(Slides address by disabling REB in the period according to the delay length)
n
−
1 cycle
n
+
1 cycle n
+
2 cycle n
+
3 cycle
0 cycle
1 cycle
2 cycle
n cycle
WCK
RCK
t
RESS
t
RESH
WRESB
RRESB
t
NREH
t
RES
REB
t
DS
t
DH
t
DS
t
DH
Dn
(0)
(1)
(2)
(n
−
2)
(n
−
1)
(n)
(n + 1)
(n + 2)
(n + 3)
m cycle
HIGH-Z
t
AC
t
OH
Qn
(0)
(1)
(2)
(3)
WEB = "L"
m
≥
3
REJ03F0255-0200 Rev.2.00 Sep 14, 2007
Page 10 of 13
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