M66257FP
Function
When write enable input
WE
is "L", the contents of data inputs D
0
to D
7
are written into 1-line delay data only memory
in synchronization with rise edge of write clock input WCK. At this time, the write address counter of 1-line delay data
only memory is also incremented simultaneously.
The write functions given below are also performed in synchronization with rise edge of WCK.
When
WE
is "H", a write operation to 1-line delay data only memory is inhibited and the write address counter of 1-line
delay data only memory is stopped.
When write reset input
WRES
is "L", the write address counter of 1-line delay data only memory is initialized.
When read enable input
RE
is "L", the contents of 1-line delay data only memory are output to data outputs Q
00
to Q
07
and those of 2-line delay data only memory to data outputs Q
10
to Q
17
in synchronization with the rise of read clock
input RCK. At this time, the read address counters of 1-line and 2-line delay data only memories is also incremented
simultaneously.
Moreover, data of Q
00
to Q
07
are written into 2-line delay data only memory in synchronization with rise edge of RCK.
At this time, the write address of 2-line delay data only memory is incremented.
The read functions given below are also performed in synchronization with rise edge of RCK.
When
RE
is "H", a read operation from both of 1-line delay data only memory and 2-line delay data only memory is
inhibited and the read address counter of each memory is stopped. The outputs of Q
00
to Q
07
and Q
10
to Q
17
are in the
high impedance state.
Moreover, a write operation to 2-line delay data only memory is inhibited and the write address counter of 2-line delay
data only memory is stopped.
When read reset input
RRES
is "L", the read address counter of 1-line delay data only memory, and the write address
counter and read address counter of 2-line delay data only memory are initialized.
REJ03F0251-0200 Rev.2.00 Sep 14, 2007
Page 4 of 12
RENESAS [ RENESAS TECHNOLOGY CORP ]
