M66257FP
5120
×
8-Bit
×
2 Line Memory (FIFO)
REJ03F0251-0200
Rev.2.00
Sep 14, 2007
Description
The M66257FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120-word
×
8-bit double
configuration which uses high-performance silicon gate CMOS process technology.
It allows simultaneous output of 1-line delay data and 2-line delay data, and is most suitable for data correction over
multiple lines.
It has separate clock, enable and reset signals for write and read, and is most suitable as a buffer memory between
devices with different data processing throughput.
Features
•
•
•
•
•
•
•
•
Memory configuration:
5120 words
×
8 bits
×
2 (dynamic memory)
High-speed cycle:
25 ns (Min)
High-speed access:
18 ns (Max)
Output hold:
3 ns (Min)
Fully independent, asynchronous write and read operations
Output:
3 states
1-line delay
Q
00
to Q
07
:
Q
10
to Q
17
:
2-line delay
Application
Digital photocopiers, high-speed facsimile, laser beam printers.
Block Diagram
Data input
D
0
to D
7
27
26
25
24
23
22
21
20
Data output
Q
00
to Q
07
2
3
4
5
6
7
8
9
Data output
Q
10
to Q
17
10
11
12
13
14
15
16
17
Input buffer
Output buffer
Read address counter
Write address counter
Read control circuit
Write control circuit
WE
32
Write
enable input
WRES
31
Write
reset input
WCK
30
Write
clock input
V
CC
18
V
CC
28
V
CC
36
35
RE
Read
enable input
(
Memory array of
5120-word
×
8-bit
×
2 configuration
1-line delay data only memory/
2-line delay data only memory
34
RRES
)
Read
reset input
33
RCK
Read
clock input
1
GND
19
GND
29
GND
REJ03F0251-0200 Rev.2.00 Sep 14, 2007
Page 1 of 12
RENESAS [ RENESAS TECHNOLOGY CORP ]
