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M66256FP 参数 Datasheet PDF下载

M66256FP图片预览
型号: M66256FP
PDF下载: 下载PDF文件 查看货源
内容描述: 5120 × 8位线存储器( FIFO) [5120 × 8-Bit Line Memory (FIFO)]
分类和应用: 存储光电二极管先进先出芯片
文件页数/大小: 14 页 / 171 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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M66256FP
Shortest Read of Data "n" Written in Cycle n
(Cycle n
1 on read side should be started after end of cycle n + 1 on write side)
When the start of cycle n
1 on read side is earlier than the end of cycle n + 1 on write side, output Qn of cycle n
becomes invalid.
In the figure shown below, the read of cycle n
1 is invalid.
Cycle n
Cycle n
+
1
Cycle n
+
2
Cycle n
+
3
WCK
Dn
(n)
(n + 1)
(n + 2)
(n + 3)
Cycle n
2
Cycle n
1
Cycle n
RCK
Qn
Invalid
(n)
Longest Read of Data "n" Written in Cycle n: 1-line Delay
(Cycle n <1>* on read side should be started when cycle n <2>* on write is started)
Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1>* and the start of writing side n cycle
<2>* overlap each other.
Cycle n <1>*
Cycle 0 <2>*
Cycle n <2>*
WCK
Dn
(n
1) <1>*
Cycle n <0>*
(n) <1>*
(00) <2>*
(n
1) <2>*
(n) <2>*
Cycle 0 <1>*
Cycle n <1>*
RCK
Qn
(n
1) <0>*
(n) <0>*
(0) <1>*
(n
1) <1>*
(n) <1>*
Note: <0>*, <1>* and <2>* indicates a line value.
REJ03F0250-0200 Rev.2.00 Sep 14, 2007
Page 11 of 13