M66256FP
N-bit Delay 2
(Sliding
WRES
and
RRES
at a cycle corresponding to delay length)
Cycle 0
Cycle 1
Cycle 2
Cycle n
−
2
Cycle n
−
1
Cycle n
Cycle n
+
1 Cycle n
+
2 Cycle n
+
3
WCK
RCK
t
RESS
t
RESH
WRES
t
RESS
t
RESH
RRES
t
DS
t
DH
t
DS
t
DH
Dn
(0)
(1)
(2)
(n
−
2)
(n
−
1)
(n)
(n + 1)
(n + 2)
(n + 3)
m cycles
t
AC
t
OH
Qn
(0)
(1)
(2)
(3)
WE, RE
= "L"
m
≥
3
N-bit Delay 3
(Disabling
RE
at a cycle corresponding to delay length)
Cycle 0
Cycle 1
Cycle 2
Cycle n
−
1
Cycle n
Cycle n
+
1 Cycle n
+
2 Cycle n
+
3
WCK
RCK
t
RESS
t
RESH
WRES
RRES
t
NREH
t
RES
RE
t
DS
t
DH
t
DS
t
DH
Dn
(0)
(1)
(2)
(n
−
2)
(n
−
1)
(n)
(n + 1)
(n + 2)
(n + 3)
m cycles
HIGH-Z
t
AC
t
OH
Qn
(0)
(1)
(2)
(3)
WE
= "L"
m
≥
3
REJ03F0250-0200 Rev.2.00 Sep 14, 2007
Page 10 of 13