M62376GP
Application Example
V
DD
V
CC
13
V
DD
DAC output
Adjustment pins
for analog IC
14
V
CC
(*)
1 A1
2 A2
3 A3
4 A4
RESET
23
EN
22
SO 21
SI 20
CLK 19
Shared pins for
DAC and I/O
DAC output
Adjustment pins
for analog IC
5 D11/A5
6 D10/A6
7 D9/A7
8 D8/A8
9 D7/A9
MCU
D0 18
D1 17
D2 16
D3 15
I/O
Logic IC
comparator
I/O
Logic IC
comparator
10 D6/A10
11 D5/A11
12 D4/A12
GND
24
Note:
The
RESET
pin is directly connected with the power pin to use power-on reset. However, when
forced reset is done from outside, the capacitance (0.1 to 10
µF)
should be connected between
RESET
pin and ground to remove noise due to installation of line, etc.
Precaution for Use
This IC has two power supply pins and a ground pin. Superimposition of these pins with ripple and spike noise may
cause reduction of conversion accuracy and occurrence of malfunction. Be sure to insert a capacitor between each
power supply and the GND pin to stabilize D/A converting operation.
The output buffer amplifier of this IC has strong characteristics against capacitive load. Accordingly, when the
capacitance (10
µF
Max) is connected between output and ground to remove jitter and noise due to installation of
output line, no problem may occur in operation of DAC. However, notice that the removal results in lengthening the
settling time.
This IC also provides power-on reset function. To assure the resetting operation, power supply should be turned on in
the order of timing shown in the diagram below.
Order: 1. V
CC
→
2. V
DD
V
DD
V
CC
Voltage
Time t
Figure 1 Order for Power-on
REJ03D0881-0300 Rev.3.00 Mar 25, 2008
Page 9 of 10
RENESAS [ RENESAS TECHNOLOGY CORP ]
