M62376GP
Block Diagram for Explanation of Terminals
V
DD
13
EN
22
CLK 19
SI 20
RESET
23
Power ON
RESET
Level shift
V
CC
14
GND
24
[1110]
Clock
control
circuit
EN
CLK
Di11 Di10 Di9 Di8 Di7 Di6 Di5 Di4 Di3 Di2 Di1 Di0
Shift register
S15 S14 S13 S12 S11 S10 S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
21 SO
Level shift
EN
Decoder (12)
Decoder (4)
EN
.........
[0000]
8-bit
latch
8-bit D/A
converter
...
...
8-bit
latch
8-bit D/A
converter
8-bit
latch
8-bit D/A
converter
............
............
8-bit
latch
8-bit D/A
converter
8-bit
latch
Level
shift
(11010000)
(A5-A12 Hi-Z)
[1111]
(8)
12
-bit
latch
− +
...
− +
− +
............
− +
(8)
Level shift
(12)
A1
A4
A5
A12
[1101]
Latch
Latch
(4)
18
D0
(8)
1
A1
......
4
A4
5
D11/A5
............
12
D4/A12
15
D3
16
D2
17
D1
Absolute Maximum Ratings
Item
Digital supply voltage
Analog supply
(D/A converter upper reference voltage)
Input voltage
Output voltage
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
Symbol
V
CC
V
DD
V
IN
Vout
V
IN
Vout
Pd
Topr
Tstg
Ratings
–0.3 to +7.0
–0.3 to +7.0
–0.3 to V
CC
+ 0.3
–0.3 to V
CC
+ 0.3
–0.3 to V
DD
+ 0.3
–0.3 to V
DD
+ 0.3
200
–20 to +85
–40 to +125
Unit
V
V
V
V
V
V
mW
°C
°C
Conditions
V
CC
supply side pin
V
CC
supply side pin
V
DD
supply side pin
V
DD
supply side pin
REJ03D0881-0300 Rev.3.00 Mar 25, 2008
Page 3 of 10
RENESAS [ RENESAS TECHNOLOGY CORP ]
