M62320P/FP
Functional Description
All parallel data I/O terminals are set to the input-state after power-on. In case any terminals need to be set to the
output state, the corresponding terminals should be set during the write mode. This setting is hold until a next setting.
In the write mode, 8 bits data can be transmitted from the I
2
C BUS interface to the parallel ports continually after the
slave address and I/O setting.
In the read mode, 8 bits data can be transmitted from the parallel ports to the I
2
C BUS interface continually after the
slave address setting.
In the case of a changing between the write-and read-mode, the data must be transmitted again from the starting
condition.
•
In a case of a data conversion from serial to parallel.
Transmission from a master (MCU etc.)
Transmission from a slave (M62320)
Start
condition
Slave address
I/O setting byte
DATA
DATA
Stop
condition
SDA
SCL
0
1
1
1
A2 A1 A0
0
A
P7 P6 P5 P4 P3 P2 P1 P0
A
D17 D16 D15 D14 D13 D12 D11 D10
A
D27 D26 D25 D24 D23 D22 D21
D20
A
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Data output
Data output
D
1X
D
2X
D0
to
D7
Hi-Z
•
In a case of a data conversion from parallel to serial.
All I/O setting resistors are set to low (input) in the write mode, before a parallel data is read. (All I/O setting
resistors are set to the input mode after power-on).
Transmission from a master (MCU etc.)
Transmission from a slave (M62320)
Start
condition
Slave address
I/O setting byte
SDA
SCL
0
1
1
1
A2 A1 A0
0
A
P7 P6 P5 P4 P3 P2 P1 P0
A
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
D0 to D7
output
Hi-Z
Start
condition
Slave address
DATA
DATA
DATA
Stop
condition
SDA
SCL
0
1
1
1
A2 A1 A0
1
A
D17 D16 D15 D14 D13 D12 D11 D10
A
D37 D36 D35 D34 D33 D32 D31 D30
A
D47 D46 D45 D44 D43 D42 D41 D40
A
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
D0 to D7
input
(example)
D0 to D7
output
D
1X
Data latch
Hi-Z
D
2X
D
3X
Data latch
D
4X
Data latch
REJ03D0863-0300 Rev.3.00 Mar 25, 2008
Page 7 of 10
RENESAS [ RENESAS TECHNOLOGY CORP ]
