M5M5256DFP-70XL 参数 Datasheet PDF下载

RENESAS LSIs

M5M5256DFP,VP-55LL,-70LL,-70LLI,

-55XL,-70XL

262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM

Write cycle ( /S control mode)

t

CW

A

0~ 14

t

su

(A)

/S

(Note 5)

t

su

(S)

t

rec

(W)

/W

(Note 3)

(Note 4)

(Note 3)

t

su

(D)

t

h

(D)

DQ

1~ 8

DATA IN

STABLE

Note 3

4

5

6

7

:

:

:

:

:

Hatching indicates the state is "don't care".

Writing is executed in ov erlap of /S and /W low.

If /W goes low simultaneously with or prior to /S, the outputs remain in the high impedance state.

Don't apply inv erted phase signal externally when DQ pin is output mode.

ten, tdis are periodically sampled and are not 100% tested.

(4) MEASUREMENT CONDITIONS

Input pulse level .............. V

IH

=2.4V,V

IL

=0.6V

Input rise and fall time ..... 5ns

Reference level ................ V

OH

=V

OL

=1.5V

Output load ...................... Fig.1 CL=50pF (-55LL,-55XL )

CL=100pF (-70LL,-70LLI,-70XL )

CL=5pF (for ten,tdis)

Transition is measured ±500mV from steady

state voltage. (for ten,tdis)

Vcc

1.8k

Ω

DQ

990

Ω

(Including

scope and JIG)

C

L

Fig.1 Output load

6