MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 2. Interrupt types and the interrupt vector addresses
INTERRUPTS
Table 2 shows the interrupt types and the corresponding interrupt
vector addresses. Reset is also treated as a type of interrupt and is
discussed in this section, too.
Interrupts
Vector addresses
00FFD216 00FFD316
00FFD416 00FFD516
____
INT4 external interrupt
____
INT3 external interrupt
A-D
DBC is an interrupt used during debugging.
00FFD616
00FFD816
00FFD716
00FFD916
Interrupts other than reset, DBC, watchdog timer, zero divide, and
BRK instruction all have interrupt control registers. Table 3 shows the
addresses of the interrupt control registers and Figure 10 shows the
bit configuration of the interrupt control register.
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
00FFDA16 00FFDB16
00FFDC16 00FFDD16
00FFDE16 00FFDF16
The interrupt request bit is automatically cleared by the hardware
during reset or when processing an interrupt. Also, interrupt request
00FFE016
00FFE216
00FFE416
00FFE616
00FFE816
00FFE116
00FFE316
00FFE516
00FFE716
00FFE916
Timer B1
bits other than DBC and watchdog timer can be cleared by software.
____ ___
Timer B0
INT4 to INT0 are external interrupts; whether to cause an interrupt at
the input level (level sense) or at the edge (edge sense) can be se-
lected with the level/edge select bit. Furthermore, the polarity of the
interrupt input can be selected with the polarity select bit.
Timer A4
Timer A3
Timer A2
00FFEA16 00FFEB16
00FFEC16 00FFED16
00FFEE16 00FFEF16
Timer A1
In the INT3 external interrupt, the INT3 input, KI3 to KI0 inputs, or KI4
____
Timer A0
____
to KI0 inputs can be selected with bits 7 and 6 of INT3 interrupt con-
trol register.
INT2 external interrupt
____
00FFF016
00FFF216
00FFF416
00FFF616
00FFF816
00FFFA16
00FFF116
00FFF316
00FFF516
00FFF716
00FFF916
00FFFB16
INT1 external interrupt
____
Timer and UART interrupts are described in the respective section.
The priority of interrupts when multiple interrupts are caused simul-
taneously is partially fixed by hardware, but, it can also be adjusted
by software as shown in Figure 11.
INT0 external interrupt
Watchdog timer
____
DBC (Do not select.)
Break instruction
Zero divide
The hardware priority is fixed as the following:
reset > DBC > watchdog timer > other interrupts
00FFFC16 00FFFD16
00FFFE16 00FFFF16
Reset
7
6
5
4
3
2
1
0
Interrupt priority level
Interrupt request bit (Note 1)
0 : No interrupt
1 : Interrupt
Interrupt control register configuration for A-D converter, UART0, UART1, timer A0 to timer A4, and timer B0 to timer B2.
Note 1: The A-D conversion interrupt request bit becomes undefined after reset. Clear this bit to “0” before use of the A-D conversion interrupt.
7
6
5
4
3
2
1
0
Interrupt priority level
Interrupt request bit
0 : No interrupt
1 : Interrupt
Polarity select bit
0 : Set interrupt request bit at “H” level for level sense and when changing from “H” to “L”
level for edge sense.
1 : Set interrupt request bit at “L” level for level sense and when changing from “L” to “H”
level for edge sense.
Level/Edge select bit
0 : Edge sense
1 : Level sense
Key input interrupt select bits 1, 0 (only for INT3 interrupt control register)
0 0 : INT3 interrupt selected
0 1 : Do not select.
1 0 : Key input interrupt (KI3 to KI0) selected
1 1 : Key input interrupt (KI4 to KI0) selected
Interrupt control register configuration for INT4– INT0 (Note 2).
Note 2: The contents of INT4 interrupt control register after reset cannot be changed unless bit 5 of the particular function select register 1 (see
Figure 15) is set to “1.”
Fig. 10 Interrupt control register bit configuration
18
RENESAS [ RENESAS TECHNOLOGY CORP ]
