REVISION DESCRIPTION LIST
M37754M8C-XXXGP/HP DATA SHEET
Rev.
Rev.
Revision Description
No.
date
1.0 First Edition
971114
1.01 (1) Page 14 is updated. (The previous version of this page cannot be read in.)
980602
(2 ) The following are added:
•MASK ROM ORDER CONFIRMATION FORM
•MARK SPECIFICATION FORM
2.00 (1) For the “valid output polarity select bit for interrupt request (bit 1 at address 1C16)” (three-
phase mode 1), it’s name and function are corrected:
990428
• New bit name in three-phase mode 1: interrupt validity output select bit
• Corrected function:
0: Timer B2 interrupt request generated at each even-numbered underflow of timer B2
1: Timer B2 interrupt request generated at each odd-numbered underflow of timer B2
• Related pages: pages 37, 38, 40
(2) For the following register, it’s internal status after reset is corrected:
• Target register: processor mode register 0 (address 5E16
• Correction: the status of bit 1 is “0”. (Not “1”.)
• Related page: page 63
)
(3) The names of registers at addresses 5C16, 5D16 are corrected:
• Address 5C16: timer B1 mode register
• Address 5D16: timer B2 mode register
• Related page: page 63
(4) For the “timer A write flag (address 4516)”, it’s name and it’s bit name are corrected:
• New register name: timer A write register
• New bit name: timer Ai write bit (i = 0 to 2)
• Related pages: pages 8, 37, 40, 63
(1/1)
RENESAS [ RENESAS TECHNOLOGY CORP ]
