欢迎访问ic37.com |
会员登录 免费注册
发布采购

M37754S4CGP 参数 Datasheet PDF下载

M37754S4CGP图片预览
型号: M37754S4CGP
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片16位CMOS微机 [SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER]
分类和应用: 微控制器和处理器外围集成电路计算机时钟
文件页数/大小: 115 页 / 1558 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
 浏览型号M37754S4CGP的Datasheet PDF文件第105页浏览型号M37754S4CGP的Datasheet PDF文件第106页浏览型号M37754S4CGP的Datasheet PDF文件第107页浏览型号M37754S4CGP的Datasheet PDF文件第108页浏览型号M37754S4CGP的Datasheet PDF文件第110页浏览型号M37754S4CGP的Datasheet PDF文件第111页浏览型号M37754S4CGP的Datasheet PDF文件第112页浏览型号M37754S4CGP的Datasheet PDF文件第113页  
MITSUBISHI MICROCOMPUTERS  
M37754M8C-XXXGP, M37754M8C-XXXHP  
M37754S4CGP, M37754S4CHP  
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER  
<NOTE> External bus timing when internal memory area is accessed (2-φ access) in high-speed  
running  
(VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) 40 MHz when the clock source select bit = “0” )  
f (XIN) = 40 MHz  
Bus timing  
data formula  
Symbol  
Parameter  
Unit  
Min.  
Max.  
1 × 109  
f(XIN)  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tw(φH), tw(φL)  
td(φ1–WR)  
td(φ1–RD)  
φ high-level pulse width, φ low-level pulse width  
5
– 20  
___  
WR output delay time  
–7  
–7  
5
12  
12  
___  
RD output delay time  
1 × 109  
– 20  
___  
__  
tw(WR)  
WR low-level pulse width  
f(XIN)  
1 × 109  
f(XIN)  
2 × 109  
f(XIN)  
2 × 109  
f(XIN)  
2 × 109  
f(XIN)  
2 × 109  
f(XIN)  
2 × 109  
f(XIN)  
2 × 109  
f(XIN)  
2 × 109  
f(XIN)  
___  
__  
tw(RD)  
RD low-level pulse width  
5
– 20  
td(A–WR)  
Address output delay time  
Address output delay time  
Address output delay time  
25  
25  
25  
10  
25  
25  
10  
– 25  
td(A–RD)  
– 25  
td(A–ALE)  
– 40  
____  
td(BHE–WR)  
td(BHE–RD)  
td(BHE–ALE)  
td(CS–WR)  
td(CS–RD)  
td(CS–ALE)  
BHE output delay time  
– 25  
____  
BHE output delay time  
– 25  
____  
BHE output delay time  
– 40  
Chip select output delay time  
Chip select output delay time  
Chip select output delay time  
Data output delay time  
– 25  
2 × 109  
f(XIN)  
2 × 109  
f(XIN)  
– 25  
– 40  
————  
t
t
d(WR–DLQ/DHQ)  
35  
1 × 109  
+ 5  
pxz(WR–DLZ/DHZ) Floating start delay time  
30  
4
f(XIN)  
————  
td(ALE–WR)  
td(ALE–RD)  
tw(ALE)  
ALE output delay ti
ALE output dela
ALE pulse width  
————  
4
1 × 109  
– 15  
10  
10  
10  
10  
10  
10  
10  
15  
0
f(XIN)  
1 × 109  
f(XIN)  
1 × 109  
f(XIN)  
1 × 109  
f(XIN)  
1 × 109  
f(XIN)  
1 × 109  
f(XIN)  
1 × 109  
f(XIN)  
1 × 109  
f(XIN)  
th(WR–A)  
Address hold time  
Address hold time  
– 15  
th(RD–A)  
– 15  
____  
td(WR–BHE)  
td(RD–BHE)  
td(WR–CS)  
td(RD–CS)  
BHE hold time  
– 15  
____  
BHE hold time  
– 15  
Chip select hold time  
Chip select hold time  
Data hold time  
– 15  
– 15  
t
t
h(WR–DLQ/DHQ)  
– 10  
pzx(WR–DLZ/DHZ) Floating release delay time  
————  
: f(XIN) 20 MHz when the clock source select bit = “1”.  
: f(XIN) = 20 MHz when the clock source select bit = “1”.  
108  
 复制成功!