FUNCTIONAL BLOCK DIAGRAM of M37274EFSP
PR
Input ports P7
0
–P7
2
Pins for data slicer
V
SS
CNV
SS
26
23
19
29
21
20
28
22
Clock input Clock output
V
HOLD
HLF
RVCO
CV
IN
30
27
18
M
ELI
X
IN
X
OUT
Reset input
RESET AV
CC
V
CC
Input ports P6
3
, P6
4
Clock input for OSD/ Clock output for OSD/
sub-clock input sub-clock output
OSC1 OSC2
24
25
.
.
tion change
ifica
pec bject to
al s
u
a fin re s
not imits a
is is tic l
Th en
m
ice:
Not e para
om
S
ARY
IN
P7 (3)
Data slicer
A-D converter
Clock
generating
circuit
TIM2
TIM3
Program
counter
Data bus
Timer count source
selection circuit
Timer 1
T1 (8)
P6 (2)
Timer 2
T2 (8)
Timer 3
T3 (8)
RAM
1024 bytes
ROM
60 K bytes
PC
L
(8)
Progam
counter
PC
H
(8)
Address bus
Timer 4
T4 (8)
Control signal
Index
register
Index
register
8-bit
arithmetic
and
logical unit
X (8)
Y (8)
Stack
pointer
S (8)
Timer 5
T5 (8)
Timer 6
T6 (8)
Accumulator
A (8)
Processor
status
register
PS (8)
Instruction
decoder
ROM
correction
function
Instruction
register (8)
CRT circuit
OUT2
INT3
INT1
INT2
Multi-master
I2C-BUS interface
A-D
converter
SI/O (8)
S
IN
S
CLK
S
OUT
P2 (8)
P0 (8)
14bit
PWM
8-bit
PWM circuit
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
SDA2
SDA1
SCL2
SCL1
P3 (2)
P1 (8)
P4 (7)
P5 (4)
OUT1
B
G
R
V
SYNC
H
SYNC
17 16 15 6 5 4 3
49 50 51 52
2
1
32
31
14 34 35 36 37 38 39 40
10 9 8 7 41 42 43 44 45 46 47 48 33 13 12 11
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
I/O ports
P3
0
, P3
1
I/O port P2
I/O port P1
I/O port P0
Input ports P4
0
–P4
6
Output port P5
Sync
signal input
3
RENESAS [ RENESAS TECHNOLOGY CORP ]
