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M37270EFSP 参数 Datasheet PDF下载

M37270EFSP图片预览
型号: M37270EFSP
PDF下载: 下载PDF文件 查看货源
内容描述: 单片8位CMOS单片机结合闭合字幕解码器和屏幕显示控制器 [SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER]
分类和应用: 解码器显示控制器瞄准线计算机
文件页数/大小: 95 页 / 1505 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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MITSUBISHI MICROCOMPUTERS  
M37270MF-XXXSP  
M37270EF-XXXSP, M37270EFSP  
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER  
and ON-SCREEN DISPLAY CONTROLLER  
(9)Timer 5 · 6 interrupt  
An interrupt is generated by an overflow of timer 5 or 6. Their  
priorities are same, and can be switched by software.  
(10)BRK instruction interrupt  
This software interrupt has the least significant priority. It does  
not have a corresponding interrupt enable bit, and it is not af-  
fected by the interrupt disable flag I (non-maskable).  
Interrupt request bit  
Interrupt enable bit  
Interrupt disable flag I  
Interrupt  
request  
BRK instruction  
Reset  
Fig. 6. Interrupt control  
7
0
7
0
Interrupt request register 1  
(IREQ1: address 00FC16)  
Interrupt request register 2  
(IREQ2: address 00FD16)  
0
Timer 1 interrupt request bit  
Timer 2 interrupt request bit  
Timer 3 interrupt request bit  
Timer 4 interrupt request bit  
OSD interrupt request bit  
VSYNC interrupt request bit  
INT1 interrupt request bit  
Data slicer interrupt request bit  
Serial I/O interrupt request bit  
f(XIN)/4096 interrupt request bit  
INT2 interrupt request bit  
Multi-master I2C-BUS  
interface interrupt request bit  
A-D conversion • INT3 interrupt  
request bit  
Timer 5 6 interrupt request bit  
Fix this bit to “0.”  
0 : No interrupt request issued  
1 : Interrupt request issued  
7
0
7
0
Interrupt control register 1  
( ICON1: address 00FE16)  
Interrupt control register 2  
( ICON2 : address 00FF16)  
Timer 1 interrupt enable bit  
Timer 2 interrupt enable bit  
Timer 3 interrupt enable bit  
Timer 4 interrupt enable bit  
OSD interrupt enable bit  
VSYNC interrupt enable bit  
INT1 interrupt enable bit  
Data slicer interrupt enable bit  
Serial I/O interrupt enable bit  
f(XIN)/4096 interrupt enable bit  
INT2 interrupt enable bit  
Multi-master I2C-BUS  
interface enable bit  
A-D conversion • INT3 interrupt  
request bit  
Timer 5 6 interrupt enable bit  
Timer 5 6 interrupt switch bit  
0 : Timer 5  
1 : Timer 6  
0 : Interrupt disabled  
1 : Interrupt enabled  
Fig. 5. Structure of interrupt-related registers  
13  
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