M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
8.10 ROM CORRECTION FUNCTION
This can correct program data in the ROM. Up to 2 addresses can be
corrected ; a program for correction is stored in the ROM correction
memory in the RAM as the top address. There are 2 vectors for ROM
correction :
ROM correction address 1 (high-order) 021716
ROM correction address 1 (low-order) 021816
ROM correction address 2 (high-order) 021916
ROM correction address 2 (low-order) 021A16
Vector 1 : address 02C016
Vector 2 : address 02E016
Set the address of the ROM data to be corrected into the ROM cor-
rection address register. When the value of the counter matches the
ROM data address in the top address of the ROM correction vector,
the main program branches to the correction program stored in the
ROM memory. To return from the correction program to the main
program, the op code and operand of the JMP instruction (total of 3
bytes) are necessary at the end of the correction program. The ROM
correction function is controlled by the ROM correction enable regis-
ter.
Fig. 8.10.1 ROM Correction Address Registers
Notes 1: Specify the first address (op code address) of each instruction as the
ROM correction address.
2: Use the JMP instruction (total of 3 bytes) to return from the correction
program to the main program.
3: Do not set the same ROM correction address to both vectors 1 and
2.
ROM Correction Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
ROM correction enable register (RCR) [Address 021B16
]
0 0
B
Name
unctions
After reset R W
F
0
0
Vector 1 enable bit (RCR0)
0: Disabled
1: Enabled
R W
1
0
Vector 2 enable bit (RCR1)
Fix these bits to “0.”
0: Disabled
1: Enabled
R W
2, 3
0
R W
4
to
7
0
Nothing is assigned. These bits are write disable bits. When
these bits are read out, the values are “0.”
R —
Fig. 8.10.2 ROM Correction Enable Register
Rev.1.00 Oct 01, 2002 page 53 of 110
REJ03B0134-0100Z
RENESAS [ RENESAS TECHNOLOGY CORP ]
