M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
Address 00FB16
CPU Mode Register
b7b6 b5b4b3 b2b1b0
1 1 1 1 1
0 0
CPU mode register (CM) [Address 00FB16
]
B
Name
Functions
After reset R W
Indeterminate
0, 1 Fix these bits to “0.”
R W
0: 0 page
1: 1 page
Stack page selection
bit (CM2) (See note)
2
1
R W
Indeterminate
Fix these bits to “1.”
R W
3 to 7
Note: This bit is set to “1” after the reset release.
Addresses 00FC16
Interrupt Request Register 1
b7b6 b5b4b3 b2b1b0
Interrupt request register 1 (IREQ1) [Address 00FC16
]
B
0
Name
Functions
After reset R W
Timer 1 interrupt
request bit (TM1R)
0
0
0
0
0
0
0
0
R
R
R
0 : No interrupt request issued
1 : Interrupt request issued
■
■
■
Timer 2 interrupt
request bit (TM2R)
0 : No interrupt request issued
1 : Interrupt request issued
1
2
3
4
Timer 3 interrupt
request bit (TM3R)
0 : No interrupt request issued
1 : Interrupt request issued
R ■
Timer 4 interrupt
request bit (TM4R)
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
■
■
■
■
OSD interrupt request
bit (CRTR)
R
R
R
R
V
SYNC interrupt
request bit (VSCR)
Multi-master I2C-BUS interface
interrupt request bit (IICR)
0 : No interrupt request issued
1 : Interrupt request issued
5
6
7
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
INT3 external interrupt
request bit (IT3R)
■: “0” can be set by software, but “1” cannot be set.
Rev.1.00 Oct 01, 2002 page 107 of 110
REJ03B0134-0100Z