MITSUBISHI MICROCOMPUTERS
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PORT FUNCTION
Port
Port D
Pin
D
0
–D
5
D
6
/CNTR0
D
7
/CNTR1
P0
0
–P0
3
Input
Output
I/O
(8)
I/O
(4)
Output structure
N-channel open-drain
I/O
unit
1
Control
instructions
SD, RD
SZD
CLD
OP0A
IAP0
Control
registers
W6
PU0, K0
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
Remark
Port P0
N-channel open-drain
4
Port P1
P1
0
–P1
3
I/O
(4)
N-channel open-drain
4
OP1A
IAP1
PU0, K0
Port P2
Port P3
(Note 1)
Port P4
(Note 2)
Port P5
(Note 2)
P2
0
/S
CK
P2
1
/S
OUT
P2
2
/S
IN
P3
0
/INT0
P3
1
/INT1
P3
2
, P3
3
P4
0
/A
IN4
–P4
3
/A
IN7
P5
0
–P5
3
Input
(3)
I/O
(4)
I/O
(4)
I/O
(4)
N-channel open-drain
3
IAP2
J1
4
OP3A
IAP3
OP4A
IAP4
OP5A
IAP5
I1, I2
Built-in key-on wakeup
function
(P3
0
/INT0, P3
1
/INT1)
N-channel open-drain
CMOS
4
4
Q2
FR0
Notes 1: The 4513 Group does not have P3
2
and P3
3
.
2: The 4513 Group does not have these ports.
DEFINITION OF CLOCK AND CYCLE
q
System clock
The system clock is the basic clock for controlling this product.
The system clock is selected by the bit 3 of the clock control reg-
ister MR.
Table Selection of system clock
Register MR
MR
3
0
1
System clock
f(X
IN
)
f(X
IN
)/2
Note: f(X
IN
)/2 is selected after system is released from reset.
q
Instruction clock
The instruction clock is a signal derived by dividing the system
clock by 3. The one instruction clock cycle generates the one
machine cycle.
q
Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
9
RENESAS [ RENESAS TECHNOLOGY CORP ]
