INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.3 Input/Output Port Related Registers
8
8.3.5 Port Input Special Function Control Register
Port Input Special Function Control Register (PICNT)
<Address: H’0080 0745>
b8
9
10
11
XSTAT
0
12
13
14
PISEL
0
b15
PIEN0
0
0
0
0
0
0
<After reset: H’00>
b
Bit Name
Function
R
0
W
0
8–10
11
No function assigned. Fix to "0".
XSTAT
0: XIN oscillating
1: XIN inactive
R(Note 1)
XIN oscillation status bit
12–13
14
No function assigned. Fix to "0".
0
0
PISEL
0: Content of port output latch
1: Port pin level
R
W
Port input data select bit
15
PIEN0
0: Disable input
1: Enable input
R
W
Port input enable bit
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
(1) XSTAT (XIN oscillation status) bit (Bit 11)
1) Conditions under which XSTAT is set to "1"
XSTAT is set to "1" upon detecting that XIN oscillation has stopped. When XIN remains at the same level for
a predetermined time (3 BCLK periods up to 4 BCLK periods), XIN oscillation is assumed to have stopped.
When operating normally, XIN changes state (high or low) once every BCLK period.
2) Conditions under which XSTAT is cleared to "0"
XSTAT is cleared to "0" by a system reset or by writing "0". If XSTAT is cleared at the same time it is set in (1)
above, the former has priority. Writing "1" to XSTAT is ignored.
3) Method for using XSTAT to detect XIN oscillation stoppage
Because the M32R/ECU internally contains a PLL, the internal clock remains active even when XIN oscilla-
tion has stopped.
By reading XSTAT without clearing it never once after reset, it is possible to know whether XIN has ever
stopped since the reset signal was deasserted. Similarly, by reading XSTAT after clearing it by writing "0", it
is possible to know the current oscillating status of XIN. (However, there must be an interval of at least 5
BCLK periods (20 CPU clock periods) between read and write.)
32180 Group User’s Manual (Rev.1.0)
8-21
RENESAS [ RENESAS TECHNOLOGY CORP ]
